From c9e99cb7b982228a7becde86d75070dc2574ebae Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 5 Jul 2020 11:52:09 +0100 Subject: [PATCH] OP_RFID needs to read SRR0/1, OP_SC needs to write --- src/soc/decoder/power_decoder2.py | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 812bf72e..220b0e68 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -639,7 +639,9 @@ class PowerDecode2(Elaboratable): comb += e.traptype.eq(TT_ILLEG) # request illegal instruction # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs - with m.If(e.insn_type == InternalOp.OP_TRAP): + # Note: OP_SC could actually be modified to just be a trap + with m.If((e.insn_type == InternalOp.OP_TRAP) | + (e.insn_type == InternalOp.OP_SC)): # TRAP write fast1 = SRR0 comb += e.write_fast1.data.eq(FastRegs.SRR0) # constant: SRR0 comb += e.write_fast1.ok.eq(1) @@ -647,6 +649,16 @@ class PowerDecode2(Elaboratable): comb += e.write_fast2.data.eq(FastRegs.SRR1) # constant: SRR1 comb += e.write_fast2.ok.eq(1) + # RFID: needs to read SRR0/1 + with m.If(e.insn_type == InternalOp.OP_RFID): + # TRAP read fast1 = SRR0 + comb += e.read_fast1.data.eq(FastRegs.SRR0) # constant: SRR0 + comb += e.read_fast1.ok.eq(1) + # TRAP read fast2 = SRR1 + comb += e.read_fast2.data.eq(FastRegs.SRR1) # constant: SRR1 + comb += e.read_fast2.ok.eq(1) + + return m # TODO: get msr, then can do privileged instruction -- 2.30.2