From ca1150c52df7f74b8dc2dc104ae1e0ec1fff681c Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Sat, 14 Nov 2020 15:15:44 -0300 Subject: [PATCH] Fix and enable the regspec test for the Shifter 1) use correct names for the Shifter ports in the regspec 2) migrate to the new OperandProducer 3) add the test on __main__ --- src/soc/experiment/test/test_compalu_multi.py | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py index b0211e0b..b2f63fe0 100644 --- a/src/soc/experiment/test/test_compalu_multi.py +++ b/src/soc/experiment/test/test_compalu_multi.py @@ -507,10 +507,10 @@ class CompUnitParallelTest: def test_compunit_regspec2_fsm(): - inspec = [('INT', 'a', '0:15'), - ('INT', 'b', '0:15'), + inspec = [('INT', 'data', '0:15'), + ('INT', 'shift', '0:15'), ] - outspec = [('INT', 'o', '0:15'), + outspec = [('INT', 'data', '0:15'), ] regspec = (inspec, outspec) @@ -523,7 +523,10 @@ def test_compunit_regspec2_fsm(): sim = Simulator(m) sim.add_clock(1e-6) - sim.add_sync_process(wrap(scoreboard_sim_fsm(dut))) + # create one operand producer for each input port + prod_a = OperandProducer(sim, dut, 0) + prod_b = OperandProducer(sim, dut, 1) + sim.add_sync_process(wrap(scoreboard_sim_fsm(dut, [prod_a, prod_b]))) sim_writer = sim.write_vcd('test_compunit_regspec2_fsm.vcd') with sim_writer: sim.run() @@ -587,4 +590,5 @@ if __name__ == '__main__': test_compunit() test_compunit_fsm() test_compunit_regspec1() + test_compunit_regspec2_fsm() test_compunit_regspec3() -- 2.30.2