From ca182cd0fa338ad39d531cb1be6a5a1bbf455771 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Wed, 26 Oct 2011 13:53:11 -0700 Subject: [PATCH] i965/vs: Implement vec4_visitor::generate_tex(). This is the part that takes the vec4_instruction IR and turns it into actual Gen ISA. v2: Add Gen4 messages, don't retype m0 to UW. Signed-off-by: Kenneth Graunke Reviewed-by: Ian Romanick --- src/mesa/drivers/dri/i965/brw_vec4.h | 4 + src/mesa/drivers/dri/i965/brw_vec4_emit.cpp | 106 ++++++++++++++++++++ 2 files changed, 110 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h index 5bf802787ba..d3505c3ba3d 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.h +++ b/src/mesa/drivers/dri/i965/brw_vec4.h @@ -549,6 +549,10 @@ public: struct brw_reg src0, struct brw_reg src1); + void generate_tex(vec4_instruction *inst, + struct brw_reg dst, + struct brw_reg src); + void generate_urb_write(vec4_instruction *inst); void generate_oword_dual_block_offsets(struct brw_reg m1, struct brw_reg index); diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp index 54bbe1347b9..c131343c155 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp @@ -354,6 +354,104 @@ vec4_visitor::generate_math2_gen4(vec4_instruction *inst, BRW_MATH_PRECISION_FULL); } +void +vec4_visitor::generate_tex(vec4_instruction *inst, + struct brw_reg dst, + struct brw_reg src) +{ + int msg_type = -1; + + if (intel->gen >= 5) { + switch (inst->opcode) { + case SHADER_OPCODE_TEX: + case SHADER_OPCODE_TXL: + if (inst->shadow_compare) { + msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE; + } else { + msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD; + } + break; + case SHADER_OPCODE_TXD: + /* There is no sample_d_c message; comparisons are done manually. */ + msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS; + break; + case SHADER_OPCODE_TXF: + msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD; + break; + case SHADER_OPCODE_TXS: + msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO; + break; + default: + assert(!"should not get here: invalid VS texture opcode"); + break; + } + } else { + switch (inst->opcode) { + case SHADER_OPCODE_TEX: + case SHADER_OPCODE_TXL: + if (inst->shadow_compare) { + msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE; + assert(inst->mlen == 3); + } else { + msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD; + assert(inst->mlen == 2); + } + break; + case SHADER_OPCODE_TXD: + /* There is no sample_d_c message; comparisons are done manually. */ + msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS; + assert(inst->mlen == 4); + break; + case SHADER_OPCODE_TXF: + msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD; + assert(inst->mlen == 2); + break; + case SHADER_OPCODE_TXS: + msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO; + assert(inst->mlen == 2); + break; + default: + assert(!"should not get here: invalid VS texture opcode"); + break; + } + } + + assert(msg_type != -1); + + if (inst->header_present) { + /* Set up an implied move from g0 to the MRF. */ + src = brw_vec8_grf(0, 0); + } + + uint32_t return_format; + + switch (dst.type) { + case BRW_REGISTER_TYPE_D: + return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32; + break; + case BRW_REGISTER_TYPE_UD: + return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32; + break; + default: + return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32; + break; + } + + brw_SAMPLE(p, + dst, + inst->base_mrf, + src, + SURF_INDEX_TEXTURE(inst->sampler), + inst->sampler, + WRITEMASK_XYZW, + msg_type, + 1, /* response length */ + inst->mlen, + inst->header_present, + BRW_SAMPLER_SIMD_MODE_SIMD4X2, + return_format); +} + void vec4_visitor::generate_urb_write(vec4_instruction *inst) { @@ -593,6 +691,14 @@ vec4_visitor::generate_vs_instruction(vec4_instruction *instruction, } break; + case SHADER_OPCODE_TEX: + case SHADER_OPCODE_TXD: + case SHADER_OPCODE_TXF: + case SHADER_OPCODE_TXL: + case SHADER_OPCODE_TXS: + generate_tex(inst, dst, src[0]); + break; + case VS_OPCODE_URB_WRITE: generate_urb_write(inst); break; -- 2.30.2