From ca18b65672b468c2a5105605f9a113aac4477b9d Mon Sep 17 00:00:00 2001
From: Luke Leighton <lkcl@lkcl.net>
Date: Tue, 27 Feb 2018 00:29:38 +0000
Subject: [PATCH] add bugzilla backlinks

---
 shakti/m_class/AXI.mdwn      | 2 +-
 shakti/m_class/RGMII.mdwn    | 2 +-
 shakti/m_class/wishbone.mdwn | 3 +--
 3 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/shakti/m_class/AXI.mdwn b/shakti/m_class/AXI.mdwn
index 534538bda..bb1827f51 100644
--- a/shakti/m_class/AXI.mdwn
+++ b/shakti/m_class/AXI.mdwn
@@ -2,5 +2,5 @@
 
 See also [[wishbone]] Bus
 
-*
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=10>
 * <https://github.com/alexforencich/verilog-axis>
diff --git a/shakti/m_class/RGMII.mdwn b/shakti/m_class/RGMII.mdwn
index 33090026c..e475a7be9 100644
--- a/shakti/m_class/RGMII.mdwn
+++ b/shakti/m_class/RGMII.mdwn
@@ -1,4 +1,4 @@
 # RGMII Gigabit Ethernet PHY
 
-* 
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=9>
 * <https://github.com/alexforencich/verilog-ethernet/blob/master/rtl/eth_mac_1g_rgmii.v>
diff --git a/shakti/m_class/wishbone.mdwn b/shakti/m_class/wishbone.mdwn
index 8606bac42..e623b71fd 100644
--- a/shakti/m_class/wishbone.mdwn
+++ b/shakti/m_class/wishbone.mdwn
@@ -1,6 +1,5 @@
 # Wishbone Bridge
 
 See also [[AXI]] Bus
-
-*
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=11>
 * <https://github.com/alexforencich/verilog-wishbone>
-- 
2.30.2