From ca18d84e3f13c50499b161fb402dc84fe8780c9c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 1 Mar 2022 17:09:07 +0000 Subject: [PATCH] add new icarus-versa-ecp5 platform in ls2.py --- runsimsoc2.sh | 2 +- simsoc.ys | 2 +- src/icarusversa.py | 24 +++++++++++++++++++++++ src/ls2.py | 48 ++++++++++++++++++++++++++++++---------------- src/simsoctb.v | 1 + 5 files changed, 58 insertions(+), 19 deletions(-) create mode 100644 src/icarusversa.py diff --git a/runsimsoc2.sh b/runsimsoc2.sh index 0fa295b..175a870 100755 --- a/runsimsoc2.sh +++ b/runsimsoc2.sh @@ -3,7 +3,7 @@ set -e LIB_DIR=./src/ecp5u -#python3 simsoc.py +python3 src/ls2.py isim yosys simsoc.ys cp ${LIB_DIR}/DDRDLLA.v DDRDLLA.v patch DDRDLLA.v < DDRDLLA.patch diff --git a/simsoc.ys b/simsoc.ys index 1a7780a..0e2c880 100644 --- a/simsoc.ys +++ b/simsoc.ys @@ -1,4 +1,4 @@ -read_ilang build/top.il +read_ilang build_simsoc/top.il read_verilog ../uart16550/rtl/verilog/raminfr.v read_verilog ../uart16550/rtl/verilog/uart_defines.v read_verilog ../uart16550/rtl/verilog/uart_rfifo.v diff --git a/src/icarusversa.py b/src/icarusversa.py new file mode 100644 index 0000000..daa95e6 --- /dev/null +++ b/src/icarusversa.py @@ -0,0 +1,24 @@ +from nmigen_boards.versa_ecp5 import VersaECP5Platform +from nmigen.build import TemplatedPlatform + + +# override Versa platform behaviour to output nothing but the ilang. +# this can then be used +class IcarusVersaPlatform(VersaECP5Platform): + @property + def required_tools(self): + return ["yosys"] + + @property + def file_templates(self): + return { + **TemplatedPlatform.build_script_templates, + "{{name}}.il": r""" + # {{autogenerated}} + {{emit_rtlil()}} + """, + } + + @property + def command_templates(self): + return [] diff --git a/src/ls2.py b/src/ls2.py index 4197bec..444fb6a 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -40,6 +40,7 @@ from nmigen_boards.arty_a7 import ArtyA7_100Platform from nmigen_boards.test.blinky import Blinky from crg import ECPIX5CRG +from icarusversa import IcarusVersaPlatform import sys import os @@ -174,16 +175,19 @@ class DDR3SoC(SoC, Elaboratable): # DRAM Module if ddr_pins is not None or fpga == 'sim': - ddrmodule = MT41K256M16(clk_freq, "1:2") # match DDR3 ASIC P/N + ddrmodule = dram_cls(clk_freq, "1:2") # match DDR3 ASIC P/N + + drs = lambda x: x + #drs = DomainRenamer("dramsync") - drs = DomainRenamer("dramsync") if fpga == 'sim': self.ddrphy = FakePHY(module=ddrmodule, settings=sim_ddr3_settings(clk_freq), - verbosity=SDRAM_VERBOSE_DBG) + verbosity=SDRAM_VERBOSE_DBG, + clk_freq=clk_freq) else: self.ddrphy = drs(ECP5DDRPHY(ddr_pins, sys_clk_freq=clk_freq)) - self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr) + self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr) dramcore = gramCore(phy=self.ddrphy, geom_settings=ddrmodule.geom_settings, @@ -236,12 +240,6 @@ class DDR3SoC(SoC, Elaboratable): comb += uartbus.dat_w.eq(self.cvtuartbus.dat_w) # drops 8..31 comb += self.cvtuartbus.dat_r.eq(uartbus.dat_r) # drops 8..31 comb += self.cvtuartbus.ack.eq(uartbus.ack) - m.submodules.arbiter = self._arbiter - m.submodules.decoder = self._decoder - if hasattr(self, "ddrphy"): - m.submodules.ddrphy = self.ddrphy - m.submodules.dramcore = self.dramcore - m.submodules.drambone = self.drambone if hasattr(self, "cpu"): m.submodules.intc = self.intc m.submodules.extcore = self.cpu @@ -252,6 +250,12 @@ class DDR3SoC(SoC, Elaboratable): comb += ibus.stall.eq(ibus.stb & ~ibus.ack) comb += dbus.stall.eq(dbus.stb & ~dbus.ack) + m.submodules.arbiter = self._arbiter + m.submodules.decoder = self._decoder + if hasattr(self, "ddrphy"): + m.submodules.ddrphy = self.ddrphy + m.submodules.dramcore = self.dramcore + m.submodules.drambone = self.drambone # add blinky lights so we know FPGA is alive if platform is not None: m.submodules.blinky = Blinky() @@ -304,6 +308,7 @@ class DDR3SoC(SoC, Elaboratable): for phase in self.dramcore.dfii._inti.phases: print ("dfi master", phase) ports += list(phase.fields.values()) + ports += [ClockSignal(), ClockSignal("dramsync"), ResetSignal()] return ports if __name__ == "__main__": @@ -316,17 +321,21 @@ if __name__ == "__main__": platform_kls = {'versa_ecp5': VersaECP5Platform, 'ulx3s': ULX3S_85F_Platform, 'arty_a7': ArtyA7_100Platform, + 'isim': IcarusVersaPlatform, 'sim': None, }[fpga] toolchain = {'arty_a7': "yosys_nextpnr", 'versa_ecp5': 'Trellis', + 'isim': 'Trellis', 'ulx3s': 'Trellis', 'sim': None, }.get(fpga, None) dram_cls = {'arty_a7': None, 'versa_ecp5': MT41K64M16, + #'versa_ecp5': MT41K256M16, 'ulx3s': None, - 'sim': None, + 'sim': MT41K256M16, + 'isim': MT41K64M16, }.get(fpga, None) if platform_kls is not None: platform = platform_kls(toolchain=toolchain) @@ -334,9 +343,9 @@ if __name__ == "__main__": platform = None # set clock frequency - clk_freq = 50e6 - #if fpga == 'sim': - #clk_freq = 100e6 + clk_freq = 70e6 + if fpga == 'sim': + clk_freq = 100e6 # select a firmware file firmware = None @@ -353,10 +362,11 @@ if __name__ == "__main__": # get DDR resource pins ddr_pins = None - if platform is not None and fpga in ['versa_ecp5', 'arty_a7']: + if platform is not None and fpga in ['versa_ecp5', 'arty_a7', 'isim']: ddr_pins = platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"}, - xdr={"clk":4, "a":4, "ba":4, "clk_en":4, + xdr={"rst": 4, "clk":4, "a":4, + "ba":4, "clk_en":4, "odt":4, "ras":4, "cas":4, "we":4, "cs": 4}) @@ -382,7 +392,11 @@ if __name__ == "__main__": if platform is not None: # build and upload it - platform.build(soc, do_program=True) + if fpga == 'isim': + platform.build(soc, do_program=False, + do_build=True, build_dir="build_simsoc") + else: + platform.build(soc, do_program=True) else: # for now, generate verilog vl = verilog.convert(soc, ports=soc.ports()) diff --git a/src/simsoctb.v b/src/simsoctb.v index 77e5035..f51ed07 100644 --- a/src/simsoctb.v +++ b/src/simsoctb.v @@ -134,6 +134,7 @@ module simsoctb; $dumpvars(0, dram_dqs); $dumpvars(0, dram_ck); $dumpvars(0, dram_cke); + $dumpvars(0, dram_cs_n); $dumpvars(0, dram_we_n); $dumpvars(0, dram_ras_n); $dumpvars(0, dram_cas_n); -- 2.30.2