From ca29d6044b4a9f1808e0c0a05763142bfae03932 Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 6 May 2022 14:45:53 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 4a6f61060..ef3fac685 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -596,4 +596,14 @@ the destination which can be automatic Store-and-increment. On top of a barrel-architecture the slowness of Memory access was not a problem because the Deterministic nature of classic -Load-Store-Increment +Load-Store-Increment can be compensated for by having 8 Memory +accesses scheduled underway and interleaved in a time-sliced +fashion with an FPU that is correspondingly 8 times faster than +Memory accesses. + +This design is almost identical to the early Vector Processors +of the late 1950s and early 1960s. The barrel-archutecture neatly +solves one of the inherent problems with those designs (memory +speed) and the presence of a full register file caters for a +second limitation of pure Memory-based Vector Processors: temporary +variables needed in the computation of -- 2.30.2