From ca38faa93b849082b900e19e01026909c9289e38 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Fri, 26 Nov 2021 20:53:28 +0000
Subject: [PATCH]

---
 openpower/sv/svp64.mdwn | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 9a1dbe94d..6d05c31da 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -429,6 +429,16 @@ augmented to 7 bits in length.
 
 `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
 
+## RM-1P-2S1D
+
+single-predicate, three registers (2 read, 1 write)
+ 
+| Field Name | Field bits | Description                 |
+|------------|------------|----------------------------|
+| Rdest_EXTRA3 | `10:12`    | extends Rdest             |
+| Rsrc1_EXTRA3 | `13:15`    | extends Rsrc1             |
+| Rsrc2_EXTRA3 | `16:18`    | extends Rsrc2             |
+
 ## RM-2P-2S1D/1S2D/3S
 
 The primary purpose for this encoding is for Twin Predication on LOAD
-- 
2.30.2