From ca474f98f2cda5cb333e9f851c7e0e31c9a6f823 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Fri, 4 Jan 2013 16:34:52 -0500 Subject: [PATCH] radeon/winsys: move radeon family/class identification to winsys MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Upcoming async dma support rely on winsys knowing about GPU families. Signed-off-by: Jerome Glisse Reviewed-by: Alex Deucher Reviewed-by: Marek Olšák --- src/gallium/drivers/r300/r300_chipset.c | 57 ++++----- src/gallium/drivers/r300/r300_chipset.h | 27 ----- src/gallium/drivers/r300/r300_emit.c | 4 +- src/gallium/drivers/r300/r300_query.c | 2 +- src/gallium/drivers/r300/r300_texture_desc.c | 12 +- src/gallium/drivers/r600/r600.h | 37 ------ src/gallium/drivers/r600/r600_asm.c | 5 +- src/gallium/drivers/r600/r600_pipe.c | 32 ++--- src/gallium/drivers/r600/r600_shader.c | 1 + src/gallium/drivers/radeonsi/r600.h | 12 -- .../winsys/radeon/drm/radeon_drm_winsys.c | 96 ++++++++++++--- .../winsys/radeon/drm/radeon_drm_winsys.h | 6 +- src/gallium/winsys/radeon/drm/radeon_winsys.h | 112 ++++++++++++++---- 13 files changed, 227 insertions(+), 176 deletions(-) diff --git a/src/gallium/drivers/r300/r300_chipset.c b/src/gallium/drivers/r300/r300_chipset.c index beaa1f46e50..11061edc590 100644 --- a/src/gallium/drivers/r300/r300_chipset.c +++ b/src/gallium/drivers/r300/r300_chipset.c @@ -22,6 +22,7 @@ * USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "r300_chipset.h" +#include "../../winsys/radeon/drm/radeon_winsys.h" #include "util/u_debug.h" #include "util/u_memory.h" @@ -62,7 +63,7 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) switch (pci_id) { #define CHIPSET(pci_id, name, chipfamily) \ case pci_id: \ - caps->family = CHIP_FAMILY_##chipfamily; \ + caps->family = CHIP_##chipfamily; \ break; #include "pci_ids/r300_pci_ids.h" #undef CHIPSET @@ -81,71 +82,71 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) switch (caps->family) { - case CHIP_FAMILY_R300: - case CHIP_FAMILY_R350: + case CHIP_R300: + case CHIP_R350: caps->high_second_pipe = TRUE; caps->num_vert_fpus = 4; caps->hiz_ram = R300_HIZ_LIMIT; caps->zmask_ram = PIPE_ZMASK_SIZE; break; - case CHIP_FAMILY_RV350: - case CHIP_FAMILY_RV370: + case CHIP_RV350: + case CHIP_RV370: caps->high_second_pipe = TRUE; caps->num_vert_fpus = 2; caps->zmask_ram = RV3xx_ZMASK_SIZE; break; - case CHIP_FAMILY_RV380: + case CHIP_RV380: caps->high_second_pipe = TRUE; caps->num_vert_fpus = 2; caps->hiz_ram = R300_HIZ_LIMIT; caps->zmask_ram = RV3xx_ZMASK_SIZE; break; - case CHIP_FAMILY_RS400: - case CHIP_FAMILY_RS600: - case CHIP_FAMILY_RS690: - case CHIP_FAMILY_RS740: + case CHIP_RS400: + case CHIP_RS600: + case CHIP_RS690: + case CHIP_RS740: break; - case CHIP_FAMILY_RC410: - case CHIP_FAMILY_RS480: + case CHIP_RC410: + case CHIP_RS480: caps->zmask_ram = RV3xx_ZMASK_SIZE; break; - case CHIP_FAMILY_R420: - case CHIP_FAMILY_R423: - case CHIP_FAMILY_R430: - case CHIP_FAMILY_R480: - case CHIP_FAMILY_R481: - case CHIP_FAMILY_RV410: + case CHIP_R420: + case CHIP_R423: + case CHIP_R430: + case CHIP_R480: + case CHIP_R481: + case CHIP_RV410: caps->num_vert_fpus = 6; caps->hiz_ram = R300_HIZ_LIMIT; caps->zmask_ram = PIPE_ZMASK_SIZE; break; - case CHIP_FAMILY_R520: + case CHIP_R520: caps->num_vert_fpus = 8; caps->hiz_ram = R300_HIZ_LIMIT; caps->zmask_ram = PIPE_ZMASK_SIZE; break; - case CHIP_FAMILY_RV515: + case CHIP_RV515: caps->num_vert_fpus = 2; caps->hiz_ram = R300_HIZ_LIMIT; caps->zmask_ram = PIPE_ZMASK_SIZE; break; - case CHIP_FAMILY_RV530: + case CHIP_RV530: caps->num_vert_fpus = 5; caps->hiz_ram = RV530_HIZ_LIMIT; caps->zmask_ram = PIPE_ZMASK_SIZE; break; - case CHIP_FAMILY_R580: - case CHIP_FAMILY_RV560: - case CHIP_FAMILY_RV570: + case CHIP_R580: + case CHIP_RV560: + case CHIP_RV570: caps->num_vert_fpus = 8; caps->hiz_ram = RV530_HIZ_LIMIT; caps->zmask_ram = PIPE_ZMASK_SIZE; @@ -153,12 +154,12 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) } caps->num_tex_units = 16; - caps->is_r400 = caps->family >= CHIP_FAMILY_R420 && caps->family < CHIP_FAMILY_RV515; - caps->is_r500 = caps->family >= CHIP_FAMILY_RV515; - caps->is_rv350 = caps->family >= CHIP_FAMILY_RV350; + caps->is_r400 = caps->family >= CHIP_R420 && caps->family < CHIP_RV515; + caps->is_r500 = caps->family >= CHIP_RV515; + caps->is_rv350 = caps->family >= CHIP_RV350; caps->z_compress = caps->is_rv350 ? R300_ZCOMP_8X8 : R300_ZCOMP_4X4; caps->dxtc_swizzle = caps->is_r400 || caps->is_r500; - caps->has_us_format = caps->family == CHIP_FAMILY_R520; + caps->has_us_format = caps->family == CHIP_R520; caps->has_tcl = caps->num_vert_fpus > 0; if (caps->has_tcl) { diff --git a/src/gallium/drivers/r300/r300_chipset.h b/src/gallium/drivers/r300/r300_chipset.h index f96cdaf2580..f8b5d4e3d3e 100644 --- a/src/gallium/drivers/r300/r300_chipset.h +++ b/src/gallium/drivers/r300/r300_chipset.h @@ -88,33 +88,6 @@ struct r300_capabilities { boolean has_us_format; }; -/* Enumerations for legibility and telling which card we're running on. */ -enum { - CHIP_FAMILY_R300 = 0, /* R3xx-based cores. */ - CHIP_FAMILY_R350, - CHIP_FAMILY_RV350, - CHIP_FAMILY_RV370, - CHIP_FAMILY_RV380, - CHIP_FAMILY_RS400, - CHIP_FAMILY_RC410, - CHIP_FAMILY_RS480, - CHIP_FAMILY_R420, /* R4xx-based cores. */ - CHIP_FAMILY_R423, - CHIP_FAMILY_R430, - CHIP_FAMILY_R480, - CHIP_FAMILY_R481, - CHIP_FAMILY_RV410, - CHIP_FAMILY_RS600, - CHIP_FAMILY_RS690, - CHIP_FAMILY_RS740, - CHIP_FAMILY_RV515, /* R5xx-based cores. */ - CHIP_FAMILY_R520, - CHIP_FAMILY_RV530, - CHIP_FAMILY_R580, - CHIP_FAMILY_RV560, - CHIP_FAMILY_RV570 -}; - void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps); #endif /* R300_CHIPSET_H */ diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c index 1700cbb4667..3f61444abea 100644 --- a/src/gallium/drivers/r300/r300_emit.c +++ b/src/gallium/drivers/r300/r300_emit.c @@ -632,7 +632,7 @@ void r300_emit_query_start(struct r300_context *r300, unsigned size, void*state) return; BEGIN_CS(size); - if (r300->screen->caps.family == CHIP_FAMILY_RV530) { + if (r300->screen->caps.family == CHIP_RV530) { OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL); } else { OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL); @@ -735,7 +735,7 @@ void r300_emit_query_end(struct r300_context* r300) if (query->begin_emitted == FALSE) return; - if (caps->family == CHIP_FAMILY_RV530) { + if (caps->family == CHIP_RV530) { if (r300->screen->info.r300_num_z_pipes == 2) rv530_emit_query_end_double_z(r300, query); else diff --git a/src/gallium/drivers/r300/r300_query.c b/src/gallium/drivers/r300/r300_query.c index 4443362d102..e338c57ed80 100644 --- a/src/gallium/drivers/r300/r300_query.c +++ b/src/gallium/drivers/r300/r300_query.c @@ -52,7 +52,7 @@ static struct pipe_query *r300_create_query(struct pipe_context *pipe, return (struct pipe_query*)q; } - if (r300screen->caps.family == CHIP_FAMILY_RV530) + if (r300screen->caps.family == CHIP_RV530) q->num_pipes = r300screen->info.r300_num_z_pipes; else q->num_pipes = r300screen->info.r300_num_gb_pipes; diff --git a/src/gallium/drivers/r300/r300_texture_desc.c b/src/gallium/drivers/r300/r300_texture_desc.c index 9493eb19c28..590f6b9a467 100644 --- a/src/gallium/drivers/r300/r300_texture_desc.c +++ b/src/gallium/drivers/r300/r300_texture_desc.c @@ -115,9 +115,9 @@ static unsigned r300_texture_get_stride(struct r300_screen *screen, unsigned level) { unsigned tile_width, width, stride; - boolean is_rs690 = (screen->caps.family == CHIP_FAMILY_RS600 || - screen->caps.family == CHIP_FAMILY_RS690 || - screen->caps.family == CHIP_FAMILY_RS740); + boolean is_rs690 = (screen->caps.family == CHIP_RS600 || + screen->caps.family == CHIP_RS690 || + screen->caps.family == CHIP_RS740); if (tex->tex.stride_in_bytes_override) return tex->tex.stride_in_bytes_override; @@ -214,7 +214,7 @@ static void r300_setup_miptree(struct r300_screen *screen, { struct pipe_resource *base = &tex->b.b; unsigned stride, size, layer_size, nblocksy, i; - boolean rv350_mode = screen->caps.family >= CHIP_FAMILY_R350; + boolean rv350_mode = screen->caps.family >= CHIP_R350; boolean aligned_for_cbzb; tex->tex.size_in_bytes = 0; @@ -353,7 +353,7 @@ static void r300_setup_hyperz_properties(struct r300_screen *screen, tex->tex.microtile) { unsigned i, pipes; - if (screen->caps.family == CHIP_FAMILY_RV530) { + if (screen->caps.family == CHIP_RV530) { pipes = screen->info.r300_num_z_pipes; } else { pipes = screen->info.r300_num_gb_pipes; @@ -414,7 +414,7 @@ static void r300_setup_tiling(struct r300_screen *screen, struct r300_resource *tex) { enum pipe_format format = tex->b.b.format; - boolean rv350_mode = screen->caps.family >= CHIP_FAMILY_R350; + boolean rv350_mode = screen->caps.family >= CHIP_R350; boolean is_zb = util_format_is_depth_or_stencil(format); boolean dbg_no_tiling = SCREEN_DBG_ON(screen, DBG_NO_TILING); diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h index b6f7d0384e2..260536ecb44 100644 --- a/src/gallium/drivers/r600/r600.h +++ b/src/gallium/drivers/r600/r600.h @@ -35,43 +35,6 @@ struct winsys_handle; -enum radeon_family { - CHIP_UNKNOWN, - CHIP_R600, - CHIP_RV610, - CHIP_RV630, - CHIP_RV670, - CHIP_RV620, - CHIP_RV635, - CHIP_RS780, - CHIP_RS880, - CHIP_RV770, - CHIP_RV730, - CHIP_RV710, - CHIP_RV740, - CHIP_CEDAR, - CHIP_REDWOOD, - CHIP_JUNIPER, - CHIP_CYPRESS, - CHIP_HEMLOCK, - CHIP_PALM, - CHIP_SUMO, - CHIP_SUMO2, - CHIP_BARTS, - CHIP_TURKS, - CHIP_CAICOS, - CHIP_CAYMAN, - CHIP_ARUBA, - CHIP_LAST, -}; - -enum chip_class { - R600, - R700, - EVERGREEN, - CAYMAN, -}; - struct r600_tiling_info { unsigned num_channels; unsigned num_banks; diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c index 268137ff2e7..ef677170a5b 100644 --- a/src/gallium/drivers/r600/r600_asm.c +++ b/src/gallium/drivers/r600/r600_asm.c @@ -40,6 +40,7 @@ static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode * return 3; switch (bc->chip_class) { + default: case R600: case R700: switch (alu->inst) { @@ -201,8 +202,8 @@ static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode * case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT: case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT: return 1; - default: R600_ERR( - "Need instruction operand number for 0x%x.\n", alu->inst); + default: + R600_ERR("Need instruction operand number for 0x%x.\n", alu->inst); } break; } diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index 7a7a4315ec8..29ef988372b 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -917,17 +917,6 @@ static int r600_init_tiling(struct r600_screen *rscreen) } } -static unsigned radeon_family_from_device(unsigned device) -{ - switch (device) { -#define CHIPSET(pciid, name, family) case pciid: return CHIP_##family; -#include "pci_ids/r600_pci_ids.h" -#undef CHIPSET - default: - return CHIP_UNKNOWN; - } -} - static uint64_t r600_get_timestamp(struct pipe_screen *screen) { struct r600_screen *rscreen = (struct r600_screen*)screen; @@ -947,24 +936,14 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws) rscreen->ws = ws; ws->query_info(ws, &rscreen->info); - rscreen->family = radeon_family_from_device(rscreen->info.pci_id); + rscreen->family = rscreen->info.family; + rscreen->chip_class = rscreen->info.chip_class; if (rscreen->family == CHIP_UNKNOWN) { fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id); FREE(rscreen); return NULL; } - /* setup class */ - if (rscreen->family >= CHIP_CAYMAN) { - rscreen->chip_class = CAYMAN; - } else if (rscreen->family >= CHIP_CEDAR) { - rscreen->chip_class = EVERGREEN; - } else if (rscreen->family >= CHIP_RV770) { - rscreen->chip_class = R700; - } else { - rscreen->chip_class = R600; - } - /* Figure out streamout kernel support. */ switch (rscreen->chip_class) { case R600: @@ -981,6 +960,9 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws) case CAYMAN: rscreen->has_streamout = rscreen->info.drm_minor >= 14; break; + default: + rscreen->has_streamout = FALSE; + break; } /* MSAA support. */ @@ -1001,6 +983,10 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws) /* We should be able to read compressed MSAA textures, but it doesn't work. */ rscreen->msaa_texture_support = MSAA_TEXTURE_SAMPLE_ZERO; break; + default: + rscreen->has_msaa = FALSE; + rscreen->msaa_texture_support = 0; + break; } if (r600_init_tiling(rscreen)) { diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c index bca62ad8494..db45dfd2266 100644 --- a/src/gallium/drivers/r600/r600_shader.c +++ b/src/gallium/drivers/r600/r600_shader.c @@ -326,6 +326,7 @@ static unsigned r600_alu_from_byte_stream(struct r600_shader_ctx *ctx, word1 = i32_from_byte_stream(bytes, &bytes_read); switch(ctx->bc->chip_class) { + default: case R600: r600_bytecode_alu_read(&alu, word0, word1); break; diff --git a/src/gallium/drivers/radeonsi/r600.h b/src/gallium/drivers/radeonsi/r600.h index 7a8ff1015d4..8f35cc26764 100644 --- a/src/gallium/drivers/radeonsi/r600.h +++ b/src/gallium/drivers/radeonsi/r600.h @@ -37,18 +37,6 @@ struct winsys_handle; -enum radeon_family { - CHIP_UNKNOWN, - CHIP_TAHITI, - CHIP_PITCAIRN, - CHIP_VERDE, - CHIP_LAST, -}; - -enum chip_class { - TAHITI, -}; - struct r600_tiling_info { unsigned num_channels; unsigned num_banks; diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index 91710fc1b20..bcfb448db5d 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -228,29 +228,97 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws) /* Check PCI ID. */ switch (ws->info.pci_id) { -#define CHIPSET(pci_id, name, family) case pci_id: +#define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break; #include "pci_ids/r300_pci_ids.h" #undef CHIPSET - ws->gen = R300; - break; -#define CHIPSET(pci_id, name, family) case pci_id: +#define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break; #include "pci_ids/r600_pci_ids.h" #undef CHIPSET - ws->gen = R600; - break; -#define CHIPSET(pci_id, name, family) case pci_id: +#define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break; #include "pci_ids/radeonsi_pci_ids.h" #undef CHIPSET - ws->gen = SI; - break; default: fprintf(stderr, "radeon: Invalid PCI ID.\n"); return FALSE; } + switch (ws->info.family) { + default: + case CHIP_UNKNOWN: + fprintf(stderr, "radeon: Unknown family.\n"); + return FALSE; + case CHIP_R300: + case CHIP_R350: + case CHIP_RV350: + case CHIP_RV370: + case CHIP_RV380: + case CHIP_RS400: + case CHIP_RC410: + case CHIP_RS480: + ws->info.chip_class = R300; + break; + case CHIP_R420: /* R4xx-based cores. */ + case CHIP_R423: + case CHIP_R430: + case CHIP_R480: + case CHIP_R481: + case CHIP_RV410: + case CHIP_RS600: + case CHIP_RS690: + case CHIP_RS740: + ws->info.chip_class = R400; + break; + case CHIP_RV515: /* R5xx-based cores. */ + case CHIP_R520: + case CHIP_RV530: + case CHIP_R580: + case CHIP_RV560: + case CHIP_RV570: + ws->info.chip_class = R500; + break; + case CHIP_R600: + case CHIP_RV610: + case CHIP_RV630: + case CHIP_RV670: + case CHIP_RV620: + case CHIP_RV635: + case CHIP_RS780: + case CHIP_RS880: + ws->info.chip_class = R600; + break; + case CHIP_RV770: + case CHIP_RV730: + case CHIP_RV710: + case CHIP_RV740: + ws->info.chip_class = R700; + break; + case CHIP_CEDAR: + case CHIP_REDWOOD: + case CHIP_JUNIPER: + case CHIP_CYPRESS: + case CHIP_HEMLOCK: + case CHIP_PALM: + case CHIP_SUMO: + case CHIP_SUMO2: + case CHIP_BARTS: + case CHIP_TURKS: + case CHIP_CAICOS: + ws->info.chip_class = EVERGREEN; + break; + case CHIP_CAYMAN: + case CHIP_ARUBA: + ws->info.chip_class = CAYMAN; + break; + case CHIP_TAHITI: + case CHIP_PITCAIRN: + case CHIP_VERDE: + ws->info.chip_class = TAHITI; + break; + } + /* Get GEM info. */ retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO, &gem_info, sizeof(gem_info)); @@ -265,7 +333,7 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws) ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN); /* Generation-specific queries. */ - if (ws->gen == R300) { + if (ws->gen == DRV_R300) { if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES, "GB pipe count", &ws->info.r300_num_gb_pipes)) @@ -276,7 +344,7 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws) &ws->info.r300_num_z_pipes)) return FALSE; } - else if (ws->gen >= R600) { + else if (ws->gen >= DRV_R600) { if (ws->info.drm_minor >= 9 && !radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS, "num backends", @@ -333,7 +401,7 @@ static void radeon_winsys_destroy(struct radeon_winsys *rws) ws->cman->destroy(ws->cman); ws->kman->destroy(ws->kman); - if (ws->gen >= R600) { + if (ws->gen >= DRV_R600) { radeon_surface_manager_free(ws->surf_man); } if (fd_tab) { @@ -394,7 +462,7 @@ static uint64_t radeon_query_timestamp(struct radeon_winsys *rws) uint64_t ts = 0; if (ws->info.drm_minor < 20 || - ws->gen < R600) { + ws->gen < DRV_R600) { assert(0); return 0; } @@ -446,7 +514,7 @@ struct radeon_winsys *radeon_drm_winsys_create(int fd) if (!ws->cman) goto fail; - if (ws->gen >= R600) { + if (ws->gen >= DRV_R600) { ws->surf_man = radeon_surface_manager_new(fd); if (!ws->surf_man) goto fail; diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h index 22983072fbb..e714127730f 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h @@ -34,9 +34,9 @@ #include "os/os_thread.h" enum radeon_generation { - R300, - R600, - SI + DRV_R300, + DRV_R600, + DRV_SI }; struct radeon_drm_winsys { diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h b/src/gallium/winsys/radeon/drm/radeon_winsys.h index 5bcbf8d16cd..d0c48224cc5 100644 --- a/src/gallium/winsys/radeon/drm/radeon_winsys.h +++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h @@ -70,6 +70,74 @@ enum radeon_bo_usage { /* bitfield */ RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE }; +enum radeon_family { + CHIP_UNKNOWN = 0, + CHIP_R300, /* R3xx-based cores. */ + CHIP_R350, + CHIP_RV350, + CHIP_RV370, + CHIP_RV380, + CHIP_RS400, + CHIP_RC410, + CHIP_RS480, + CHIP_R420, /* R4xx-based cores. */ + CHIP_R423, + CHIP_R430, + CHIP_R480, + CHIP_R481, + CHIP_RV410, + CHIP_RS600, + CHIP_RS690, + CHIP_RS740, + CHIP_RV515, /* R5xx-based cores. */ + CHIP_R520, + CHIP_RV530, + CHIP_R580, + CHIP_RV560, + CHIP_RV570, + CHIP_R600, + CHIP_RV610, + CHIP_RV630, + CHIP_RV670, + CHIP_RV620, + CHIP_RV635, + CHIP_RS780, + CHIP_RS880, + CHIP_RV770, + CHIP_RV730, + CHIP_RV710, + CHIP_RV740, + CHIP_CEDAR, + CHIP_REDWOOD, + CHIP_JUNIPER, + CHIP_CYPRESS, + CHIP_HEMLOCK, + CHIP_PALM, + CHIP_SUMO, + CHIP_SUMO2, + CHIP_BARTS, + CHIP_TURKS, + CHIP_CAICOS, + CHIP_CAYMAN, + CHIP_ARUBA, + CHIP_TAHITI, + CHIP_PITCAIRN, + CHIP_VERDE, + CHIP_LAST, +}; + +enum chip_class { + CLASS_UNKNOWN = 0, + R300, + R400, + R500, + R600, + R700, + EVERGREEN, + CAYMAN, + TAHITI, +}; + struct winsys_handle; struct radeon_winsys_cs_handle; @@ -79,27 +147,29 @@ struct radeon_winsys_cs { }; struct radeon_info { - uint32_t pci_id; - uint32_t gart_size; - uint32_t vram_size; - - uint32_t drm_major; /* version */ - uint32_t drm_minor; - uint32_t drm_patchlevel; - - uint32_t r300_num_gb_pipes; - uint32_t r300_num_z_pipes; - - uint32_t r600_num_backends; - uint32_t r600_clock_crystal_freq; - uint32_t r600_tiling_config; - uint32_t r600_num_tile_pipes; - uint32_t r600_backend_map; - boolean r600_backend_map_valid; - boolean r600_virtual_address; - uint32_t r600_va_start; - uint32_t r600_ib_vm_max_size; - uint32_t r600_max_pipes; + uint32_t pci_id; + enum radeon_family family; + enum chip_class chip_class; + uint32_t gart_size; + uint32_t vram_size; + + uint32_t drm_major; /* version */ + uint32_t drm_minor; + uint32_t drm_patchlevel; + + uint32_t r300_num_gb_pipes; + uint32_t r300_num_z_pipes; + + uint32_t r600_num_backends; + uint32_t r600_clock_crystal_freq; + uint32_t r600_tiling_config; + uint32_t r600_num_tile_pipes; + uint32_t r600_backend_map; + uint32_t r600_va_start; + uint32_t r600_ib_vm_max_size; + uint32_t r600_max_pipes; + boolean r600_backend_map_valid; + boolean r600_virtual_address; }; enum radeon_feature_id { -- 2.30.2