From ca52aa5b8c1998a54eba5faf060848e52f9bf2a1 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Thu, 26 Feb 2015 20:22:22 -0700 Subject: [PATCH] add fpgaprog programmer --- mibuild/xilinx/programmer.py | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/mibuild/xilinx/programmer.py b/mibuild/xilinx/programmer.py index 50e98b4a..eb9f5141 100644 --- a/mibuild/xilinx/programmer.py +++ b/mibuild/xilinx/programmer.py @@ -45,6 +45,24 @@ class XC3SProg(GenericProgrammer): flash_proxy = self.find_flash_proxy() subprocess.call(["xc3sprog", "-v", "-c", self.cable, "-I"+flash_proxy, "{}:w:0x{:x}:BIN".format(data_file, address)]) + +class FpgaProg(GenericProgrammer): + needs_bitreverse = False + + def __init__(self, flash_proxy_basename=None): + GenericProgrammer.__init__(self, flash_proxy_basename) + + def load_bitstream(self, bitstream_file): + subprocess.call(["fpgaprog", "-v", "-f", bitstream_file]) + + def flash(self, address, data_file): + if address != 0: + raise ValueError("fpga prog needs a main bitstream at address 0") + flash_proxy = self.find_flash_proxy() + subprocess.call(["fpgaprog", "-v", "-sa", "-r", "-b", flash_proxy, + "-f", data_file]) + + def _run_vivado(cmds): with subprocess.Popen("vivado -mode tcl", stdin=subprocess.PIPE, shell=True) as process: process.stdin.write(cmds.encode("ASCII")) -- 2.30.2