From ca5686284f66fe1726ec0d6cedfe9b6af9f21c43 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 4 May 2023 19:33:59 +0100 Subject: [PATCH] --- openpower/sv/mv.swizzle.mdwn | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openpower/sv/mv.swizzle.mdwn b/openpower/sv/mv.swizzle.mdwn index 75cc582d2..9a09735ed 100644 --- a/openpower/sv/mv.swizzle.mdwn +++ b/openpower/sv/mv.swizzle.mdwn @@ -276,22 +276,22 @@ For a separate source/dest SUBVL (again, no elwidth overrides): if outer: for j in range(dst_subvl): for i in range(VL): - .... + yield j*VL+i else: for i in range(VL): for j in range(dst_subvl): - .... + yield i*dst_subvl+j # yield an outer-SUBVL or inner VL loop with SUBVL def index_src(outer): if outer: for j in range(SUBVL): for i in range(VL): - .... + yield j*VL+i else: for i in range(VL): for j in range(SUBVL): - .... + yield i*SUBVL+j ``` "yield" from python is used here for simplicity and clarity. -- 2.30.2