From ca5c72132f12d0a9051905e02e63552b8ba0a1e1 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 26 Jan 2020 13:05:34 +0000 Subject: [PATCH] --- 3d_gpu/architecture.mdwn | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/3d_gpu/architecture.mdwn b/3d_gpu/architecture.mdwn index ccf7671b9..83f9c3f8e 100644 --- a/3d_gpu/architecture.mdwn +++ b/3d_gpu/architecture.mdwn @@ -31,3 +31,11 @@ Dynamically. This means that in low clock rate modes the length of the whole pipeline may be reduced in latency (the number of effective stages is halved). Whilst in higher clock rate modes where the long stage latency would otherwise be a serious limiting factor, the intermediary latches are enabled, thus doubling the pipeline length into much shorter stages with lower latency, and the problem is solved. The only reason why this ingenious and elegant trick (deployed first by IBM in the 1990s) can be considered is down to the fact that the 6600 Style Dependency Matrices do not care about actual completion time, they only care about availability of the result. + +# Memory and Cache arrangement + +Section TODO, with own page [[3d_gpu/architecture/memory_and_cache]] LD/ST accesses are controlled by the 6600-style Dependency Matrices + +# Bus arrangement + +Wishbone was chosen. to expand why (related to patents). -- 2.30.2