From ca5d2b467de6a0302dc87e34a9356d74cd1df2a9 Mon Sep 17 00:00:00 2001
From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Sat, 18 Jun 2022 20:49:30 +0300
Subject: [PATCH] ppc/svp64: introduce svp64_assemble stub

---
 gas/config/tc-ppc-svp64.c | 28 ++++++++++++++++++++++++++++
 gas/config/tc-ppc.c       | 16 ++++++++++++++++
 2 files changed, 44 insertions(+)
 create mode 100644 gas/config/tc-ppc-svp64.c

diff --git a/gas/config/tc-ppc-svp64.c b/gas/config/tc-ppc-svp64.c
new file mode 100644
index 00000000000..f07115df3ce
--- /dev/null
+++ b/gas/config/tc-ppc-svp64.c
@@ -0,0 +1,28 @@
+/* tc-ppc-svp64.c -- Assemble for the PowerPC SVP64 extension.
+   Copyright (C) 2022 Free Software Foundation, Inc.
+   Written by Dmitry Selyutin aka ghostmansd.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+static void
+svp64_assemble (char *str)
+{
+  as_warn (_("opcode ignored"));
+  memcpy (str, "nop", sizeof ("nop"));
+  md_assemble (str);
+}
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 31f096eeff8..e7bcde73417 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -36,6 +36,8 @@
 #include "libxcoff.h"
 #endif
 
+#include "tc-ppc-svp64.c"
+
 /* This is the assembler for the PowerPC or POWER (RS/6000) chips.  */
 
 /* Tell the main code what the endianness is.  */
@@ -3278,6 +3280,13 @@ parse_tls_arg (char **str, const expressionS *exp, struct ppc_fixup *tls_fix)
 }
 #endif
 
+static inline bool
+is_svp64_insn (char *str)
+{
+  return (((ppc_cpu & PPC_OPCODE_SVP64) == PPC_OPCODE_SVP64) &&
+      (strncmp (str, "sv.", (sizeof ("sv.") - 1)) == 0));
+}
+
 /* This routine is called for each instruction to be assembled.  */
 
 void
@@ -3306,6 +3315,12 @@ md_assemble (char *str)
   opcode = (const struct powerpc_opcode *) str_hash_find (ppc_hash, str);
   if (opcode == (const struct powerpc_opcode *) NULL)
     {
+      if (is_svp64_insn (str))
+        {
+          svp64_assemble (str);
+          return;
+        }
+
       as_bad (_("unrecognized opcode: `%s'"), str);
       ppc_clear_labels ();
       return;
@@ -4124,6 +4139,7 @@ md_assemble (char *str)
       fixP->fx_pcrel_adjust = fixups[i].opindex;
     }
 }
+
 
 #ifdef OBJ_ELF
 /* For ELF, add support for SHT_ORDERED.  */
-- 
2.30.2