From ca640b4f87d3ce86360dcaa17e9f17ea459f6da3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 30 Oct 2018 06:09:50 +0000 Subject: [PATCH] on scalar redirected reg, break hardware loop at first dest-store --- riscv/insn_template_sv.cc | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc index 55c225b..738d3b4 100644 --- a/riscv/insn_template_sv.cc +++ b/riscv/insn_template_sv.cc @@ -225,14 +225,22 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc) #endif #include INCLUDEFILE #ifdef DEST_PREDINT +#ifndef INSN_TYPE_C_STACK_ST // XXX TODO: stack-based DEST_REG + reg_spec_t rdr = insn._DEST_REG(); + bool dest_predicated = (dest_pred & (1<<*dest_offs)) != 0; // don't check inversion here as dest_pred has already been inverted - if (zeroing && ((dest_pred & (1<<*dest_offs)) == 0)) + if (zeroing && (!dest_predicated)) { // insn._rd() would be predicated: have to use insn._rd() here -#ifndef INSN_TYPE_C_STACK_ST - WRITE_REG(insn._DEST_REG(), 0); -#endif + WRITE_REG(rdr, 0); } + else if (!zeroing && dest_predicated && !rdr.isvec) + { + // zeroing not set, answer was stored, and it's a scalar operand. + // time to exit the loop. + break; + } +#endif #endif if (vlen > 1) { -- 2.30.2