From ca7056b07fb90b9424fa33918b5d701577e23be9 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Thu, 16 Feb 2012 18:34:32 +0100
Subject: [PATCH] fhdl: support forwarding of bidirectional signals from
 instance ports

---
 examples/lm32_inst.py   |  7 +++----
 migen/fhdl/structure.py |  3 ++-
 migen/fhdl/tools.py     |  6 ++++--
 migen/fhdl/verilog.py   | 11 +++++++----
 4 files changed, 16 insertions(+), 11 deletions(-)

diff --git a/examples/lm32_inst.py b/examples/lm32_inst.py
index b4685d52..678dca55 100644
--- a/examples/lm32_inst.py
+++ b/examples/lm32_inst.py
@@ -32,10 +32,9 @@ class LM32:
 			("D_ACK_I", BV(1)),
 			("D_ERR_I", BV(1)),
 			("D_RTY_I", BV(1))],
-			[],
-			"clk_i",
-			"rst_i",
-			"lm32")
+			clkport="clk_i",
+			rstport="rst_i",
+			name="lm32")
 	
 	def get_fragment(self):
 		return Fragment(instances=[self.inst])
diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index 8a676e94..fac607cd 100644
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -209,7 +209,7 @@ class Case:
 #
 
 class Instance:
-	def __init__(self, of, outs=[], ins=[], parameters=[], clkport="", rstport="", name=""):
+	def __init__(self, of, outs=[], ins=[], inouts=[], parameters=[], clkport="", rstport="", name=""):
 		self.of = of
 		if name:
 			self.name_override = name
@@ -224,6 +224,7 @@ class Instance:
 				raise TypeError
 		self.outs = dict(map(process_io, outs))
 		self.ins = dict(map(process_io, ins))
+		self.inouts = dict(map(process_io, inouts))
 		self.parameters = parameters
 		self.clkport = clkport
 		self.rstport = rstport
diff --git a/migen/fhdl/tools.py b/migen/fhdl/tools.py
index 897ebe58..bd8393d5 100644
--- a/migen/fhdl/tools.py
+++ b/migen/fhdl/tools.py
@@ -73,9 +73,9 @@ def group_by_targets(sl):
 			groups.append((targets, [statement]))
 	return groups
 
-def list_inst_ios(i, ins, outs):
+def list_inst_ios(i, ins, outs, inouts):
 	if isinstance(i, Fragment):
-		return list_inst_ios(i.instances, ins, outs)
+		return list_inst_ios(i.instances, ins, outs, inouts)
 	else:
 		l = []
 		for x in i:
@@ -83,6 +83,8 @@ def list_inst_ios(i, ins, outs):
 				l += x.ins.values()
 			if outs:
 				l += x.outs.values()
+			if inouts:
+				l += x.inouts.values()
 		return set(l)
 
 def list_mem_ios(m, ins, outs):
diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 4af82bd5..3b6655e7 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -103,8 +103,9 @@ def _list_comb_wires(f):
 	return r
 
 def _printheader(f, ios, name, ns):
-	sigs = list_signals(f) | list_inst_ios(f, True, True) | list_mem_ios(f, True, True)
-	inst_mem_outs = list_inst_ios(f, False, True) | list_mem_ios(f, False, True)
+	sigs = list_signals(f) | list_inst_ios(f, True, True, True) | list_mem_ios(f, True, True)
+	inst_mem_outs = list_inst_ios(f, False, True, False) | list_mem_ios(f, False, True)
+	inouts = list_inst_ios(f, False, False, True)
 	targets = list_targets(f) | inst_mem_outs
 	wires = _list_comb_wires(f) | inst_mem_outs
 	r = "module " + name + "(\n"
@@ -113,7 +114,9 @@ def _printheader(f, ios, name, ns):
 		if not firstp:
 			r += ",\n"
 		firstp = False
-		if sig in targets:
+		if sig in inouts:
+			r += "\tinout " + _printsig(ns, sig)
+		elif sig in targets:
 			if sig in wires:
 				r += "\toutput " + _printsig(ns, sig)
 			else:
@@ -230,7 +233,7 @@ def convert(f, ios=set(), name="top",
 	ios |= f.pads
 
 	ns = build_namespace(list_signals(f) \
-		| list_inst_ios(f, True, True) \
+		| list_inst_ios(f, True, True, True) \
 		| list_mem_ios(f, True, True) \
 		| ios)
 
-- 
2.30.2