From ca78d4589d326f4f57b423d755ab53d9511d188a Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Wed, 24 Feb 2021 19:40:53 +0100 Subject: [PATCH] update mmu testcase --- src/soc/fu/mmu/test/test_issuer_mmu_rom.py | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/src/soc/fu/mmu/test/test_issuer_mmu_rom.py b/src/soc/fu/mmu/test/test_issuer_mmu_rom.py index b1d69f6c..640f8ed8 100644 --- a/src/soc/fu/mmu/test/test_issuer_mmu_rom.py +++ b/src/soc/fu/mmu/test/test_issuer_mmu_rom.py @@ -1,5 +1,5 @@ from nmigen import Module, Signal -from soc.simple.test.test_runner_mmu_rom import TestRunner +from soc.simple.test.test_runner import TestRunner from soc.simulator.program import Program from soc.config.endian import bigendian import unittest @@ -44,28 +44,25 @@ class MMUTestCase(TestAccumulatorBase): initial_regs = [0] * 32 + # set process table prtbl = 0x1000000 initial_regs[1] = prtbl + initial_sprs = {} self.add_case(Program(lst, bigendian), initial_regs, initial_sprs) -class RomDBG(): - def __init__(self): - self.rom = default_mem - self.debug = open("/tmp/rom.log","w") - - # yield mmu.rin.prtbl.eq(0x1000000) # set process table -- SPR_PRTBL = 720 -rom_dbg = RomDBG() if __name__ == "__main__": unittest.main(exit=False) suite = unittest.TestSuite() suite.addTest(TestRunner(MMUTestCase().test_data, microwatt_mmu=True, - rom=rom_dbg)) + rom=default_mem)) runner = unittest.TextTestRunner() runner.run(suite) + +# soc/simple/test/test_runner.py -- 2.30.2