From ca7e3a518cdf448fee69af83a0232f6bfe1d0bad Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 1 Apr 2023 20:52:38 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls010.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn index d901a720a..d0c808437 100644 --- a/openpower/sv/rfc/ls010.mdwn +++ b/openpower/sv/rfc/ls010.mdwn @@ -212,7 +212,7 @@ Performance designs. For a comparative data point the VSR Registers may be expressed in the same fashion. The c code below is directly an expression of Figure 97 in Power ISA Public v3.1 Book I Section 6.3 page 258, *after compensating for -MSB0 numbering in both bits abd elements, adapting in full to LSB0 numbering, +MSB0 numbering in both bits and elements, adapting in full to LSB0 numbering, and obeying LE ordering*. **Crucial to understanding why the subtraction from 1,3,7,15 is present -- 2.30.2