From ca7ed280333f9e8118af44b04c5b1d8b2d769cbd Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 10 Sep 2021 11:52:53 +0100 Subject: [PATCH] --- openpower/sv/cr_ops.mdwn | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn index cbd3edfe7..9dfc91e3d 100644 --- a/openpower/sv/cr_ops.mdwn +++ b/openpower/sv/cr_ops.mdwn @@ -19,15 +19,15 @@ results that also, as an aside, produce a corresponding CR Field (such as when Rc=1). Instructions that involve Rc=1 are definitively arithmetic in nature, where the corresponding Condition Register Field can be considered to -be a "co-result". Thus, if the arithmetic result is Vectorised, so -is the CR Field "co-result", which puts both firmly out of scope for +be a "co-result". Such CR Field "co-result" arithmeric operations +are firmly out of scope for this section. -Examples of v3.0B instructions to which this section does -apply is `mfcr` (3 bit operands) and `crnor` (5 bit operands). -Examples to which this section does **not** apply include -`fadds.` and `subf.` which both produce arithmetic results -(and a CR Field co-result). +* Examples of v3.0B instructions to which this section does + apply is `mfcr` (3 bit operands) and `crnor` (5 bit operands). +* Examples to which this section does **not** apply include + `fadds.` and `subf.` which both produce arithmetic results + (and a CR Field co-result). Other modes are still applicable and include: -- 2.30.2