From ca81511db518c177bfda6637cd43ae9bdf1e3abb Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 27 Apr 2022 15:16:04 +0100 Subject: [PATCH] --- openpower/sv/biginteger/analysis.mdwn | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn index 1d8fe9dc2..8b24b3753 100644 --- a/openpower/sv/biginteger/analysis.mdwn +++ b/openpower/sv/biginteger/analysis.mdwn @@ -109,7 +109,7 @@ and an OR, all of which are standard Scalar Power ISA instructions that when Vectorised are exactly what is needed. ``` -void biglsh(unsigned s, unsigned vn[], unsigned const v[], int n) +void biglsh(unsigned s, uint64_t vn[], uint64_t const v[], int n) { for (int i = n - 1; i > 0; i--) vn[i] = ((unsigned long long)v[i] << s) | (v[i - 1] >> (32 - s)); @@ -117,6 +117,10 @@ void biglsh(unsigned s, unsigned vn[], unsigned const v[], int n) } ``` +With SVP64 being on top of the standard scalar regfile the offset by +one of the elements may be achieved simply by referencing the same +vector data offset by one. + The reason why three instructions are needed instead of one in the case of big-add is because multiple bits chain through to the next element, where for add it is a single bit (carry-in, carry-out), -- 2.30.2