From ca85171dbdc2dbaf0a1754325a04ef715a8930f5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 10 May 2021 18:03:24 +0100 Subject: [PATCH] fix MemException, return correct address in DAR --- src/openpower/decoder/isa/mem.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/openpower/decoder/isa/mem.py b/src/openpower/decoder/isa/mem.py index 603d1923..64309477 100644 --- a/src/openpower/decoder/isa/mem.py +++ b/src/openpower/decoder/isa/mem.py @@ -73,11 +73,12 @@ class Mem: instr_fetch=False): print("ld from addr 0x{:x} width {:d}".format(address, width), swap, check_in_mem, instr_fetch) + ldaddr = address remainder = address & (self.bytes_per_word - 1) address = address >> self.word_log2 if remainder & (width - 1) != 0: exc = MemException("unaligned", "Unaligned access Error") - exc.dar = address + exc.dar = ldaddr raise exc if address in self.mem: val = self.mem[address] @@ -105,7 +106,7 @@ class Mem: "memaddr 0x{:x}/{:x}".format(v, staddr, addr, remainder, swap)) if remainder & (width - 1) != 0: exc = MemException("unaligned", "Unaligned access Error") - exc.dar = address + exc.dar = staddr raise exc if swap: v = swap_order(v, width) -- 2.30.2