From cab5e78cb06816c8fc6e853598761cf6fb9579e9 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 17 Dec 2020 14:32:50 +0000 Subject: [PATCH] --- openpower/sv/ldst.mdwn | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn index 3b8767e8d..4167a0498 100644 --- a/openpower/sv/ldst.mdwn +++ b/openpower/sv/ldst.mdwn @@ -20,7 +20,7 @@ and for immediate variants: Thus in the first example, the source registers may each be independently marked as scalar or vector, and likewise the destination; in the second example only the one source and one dest may be marked as scalar or vector. -Thus we can see that Vector Indexed may be covered, but there is not a convenient way to provide both fixed and element strided. This is a known limitation of retro-fitting an existing scalar ISA with Vectorisation. The solution requires an operation that has both RA, RB and an immediate. +Thus we can see that Vector Indexed may be covered, and, as demonstrated with the pseudocode below, the immediate can be set to the element width in order to give unit stride. At the minimum however it is possible to provide unit stride and vector mode, as follows: @@ -36,9 +36,12 @@ At the minimum however it is possible to provide unit stride and vector mode, as if (RA.isvec) # indirect mode (multi mode) EA = ireg[rsv+i] + immed; - else - # unit stride mode + elif (RT.isvec) + # unit and element stride mode EA = ireg[rsv] + i * immed + else + # standard scalar mode (but predicated) + EA = ireg[rsv] + immed ireg[rdv+j] <= MEM[EA]; if (!RA.isvec && !RT.isvec) break # scalar-scalar @@ -54,7 +57,7 @@ Indexed LD is:  ps = get_pred_val(FALSE, RA); # predication on src  pd = get_pred_val(FALSE, RT); # ... AND on dest  for (i=0, j=0, k=0; i < VL && j < VL && k < VL): - # skip nonpredicates elements + # skip nonpredicated RA, RB and RT if (RA.isvec) while (!(ps & 1<