From cab9e1df4d30c129e75e8a0ee575a821ab6342cf Mon Sep 17 00:00:00 2001 From: Matthew Wahab Date: Fri, 23 Sep 2016 10:57:20 +0000 Subject: [PATCH] [PATCH 17/17][ARM] Add tests for NEON FP16 ACLE intrinsics. testsuite/ 2016-09-23 Matthew Wahab * gcc.target/advsimd-intrinsics/advsimd-intrinsics.exp: Enable -march=armv8.2-a+fp16 when supported by the hardware. * gcc.target/aarch64/advsimd-intrinsics/binary_op_float.inc: New. * gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc: Add F16 tests, enabled if macro HAS_FLOAT16_VARIANT is defined. Add semi-colons to a macro invocations. * gcc.target/aarch64/advsimd-intrinsics/cmp_fp_op.inc: Add F16 tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is defined. * gcc.target/aarch64/advsimd-intrinsics/cmp_op.inc: Likewise. * gcc.target/aarch64/advsimd-intrinsics/cmp_zero_op.inc: New. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vabd.c: Add F16 tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is defined. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vabs.c: Likewise. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vadd.c: Likewise. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcage.c: Likewise. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcagt.c: Likewise. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcale.c: Likewise. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcalt.c: Likewise. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vceq.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vceqz_1.c: New. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcge.c: Add F16 tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is defined. * gcc.target/aarch64/advsimd-intrinsics/vcgez_1.c: New. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcgt.c: Add F16 tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is defined. * gcc.target/aarch64/advsimd-intrinsics/vcgtz_1.c: New. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcle.c: Add F16 tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is defined. * gcc.target/aarch64/advsimd-intrinsics/vclez_1.c: New. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vclt.c: Add F16 tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is defined. * gcc.target/aarch64/advsimd-intrinsics/vcltz_1.c: New. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcvt.c: Add F16 tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is defined. Also fix some white-space. * gcc.target/aarch64/advsimd-intrinsics/vcvtX.inc: New. * gcc.target/aarch64/advsimd-intrinsics/vcvta_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtm_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtp_1.c: New. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vfma.c: Add F16 tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is defined. Also fix some long lines and white-space. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vfms.c: Add F16 tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is defined. Also fix some long lines and white-space. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vmax.c: Add F16 tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is defined. * gcc.target/aarch64/advsimd-intrinsics/vmaxnm_1.c: New. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vmin.c: Add F16 tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is defined. * gcc.target/aarch64/advsimd-intrinsics/vminnm_1.c: New. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vmul.c: Add F16 tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is defined. * gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c: Likewise. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vmul_n.c: Likewise. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vneg.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc: Likewise. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vpadd.c: Likewise. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vpmax.c: Likewise. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vpmin.c: Likewise. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrecpe.c: Likewise. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrecps.c: Likewise. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrnd.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vrndX.inc: Likewise. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrnda.c: Likewise. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrndm.c: Likewise. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrndn.c: Likewise. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrndp.c: Likewise. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrndx.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c: Likewise. * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vsub.c: Likewise. From-SVN: r240427 --- gcc/testsuite/ChangeLog | 98 +++++++++ .../advsimd-intrinsics/advsimd-intrinsics.exp | 5 +- .../advsimd-intrinsics/binary_op_float.inc | 170 ++++++++++++++++ .../advsimd-intrinsics/binary_op_no64.inc | 57 +++++- .../aarch64/advsimd-intrinsics/cmp_fp_op.inc | 41 ++++ .../aarch64/advsimd-intrinsics/cmp_op.inc | 80 ++++++++ .../advsimd-intrinsics/cmp_zero_op.inc | 111 ++++++++++ .../aarch64/advsimd-intrinsics/vabd.c | 57 +++++- .../aarch64/advsimd-intrinsics/vabs.c | 28 +++ .../aarch64/advsimd-intrinsics/vadd.c | 31 +++ .../aarch64/advsimd-intrinsics/vcage.c | 10 + .../aarch64/advsimd-intrinsics/vcagt.c | 10 + .../aarch64/advsimd-intrinsics/vcale.c | 10 + .../aarch64/advsimd-intrinsics/vcalt.c | 10 + .../aarch64/advsimd-intrinsics/vceq.c | 18 ++ .../aarch64/advsimd-intrinsics/vceqz_1.c | 27 +++ .../aarch64/advsimd-intrinsics/vcge.c | 22 ++ .../aarch64/advsimd-intrinsics/vcgez_1.c | 30 +++ .../aarch64/advsimd-intrinsics/vcgt.c | 21 ++ .../aarch64/advsimd-intrinsics/vcgtz_1.c | 28 +++ .../aarch64/advsimd-intrinsics/vcle.c | 22 ++ .../aarch64/advsimd-intrinsics/vclez_1.c | 29 +++ .../aarch64/advsimd-intrinsics/vclt.c | 21 ++ .../aarch64/advsimd-intrinsics/vcltz_1.c | 27 +++ .../aarch64/advsimd-intrinsics/vcvt.c | 189 +++++++++++++++++- .../aarch64/advsimd-intrinsics/vcvtX.inc | 113 +++++++++++ .../aarch64/advsimd-intrinsics/vcvta_1.c | 33 +++ .../aarch64/advsimd-intrinsics/vcvtm_1.c | 33 +++ .../aarch64/advsimd-intrinsics/vcvtp_1.c | 33 +++ .../aarch64/advsimd-intrinsics/vfma.c | 46 ++++- .../aarch64/advsimd-intrinsics/vfms.c | 45 ++++- .../aarch64/advsimd-intrinsics/vmax.c | 33 +++ .../aarch64/advsimd-intrinsics/vmaxnm_1.c | 47 +++++ .../aarch64/advsimd-intrinsics/vmin.c | 37 ++++ .../aarch64/advsimd-intrinsics/vminnm_1.c | 51 +++++ .../aarch64/advsimd-intrinsics/vmul.c | 35 ++++ .../aarch64/advsimd-intrinsics/vmul_lane.c | 37 ++++ .../aarch64/advsimd-intrinsics/vmul_n.c | 32 +++ .../aarch64/advsimd-intrinsics/vneg.c | 29 +++ .../aarch64/advsimd-intrinsics/vpXXX.inc | 15 ++ .../aarch64/advsimd-intrinsics/vpadd.c | 3 + .../aarch64/advsimd-intrinsics/vpmax.c | 3 + .../aarch64/advsimd-intrinsics/vpmin.c | 3 + .../aarch64/advsimd-intrinsics/vrecpe.c | 125 ++++++++++++ .../aarch64/advsimd-intrinsics/vrecps.c | 98 +++++++++ .../aarch64/advsimd-intrinsics/vrnd.c | 8 + .../aarch64/advsimd-intrinsics/vrndX.inc | 20 ++ .../aarch64/advsimd-intrinsics/vrnda.c | 9 + .../aarch64/advsimd-intrinsics/vrndm.c | 9 + .../aarch64/advsimd-intrinsics/vrndn.c | 9 + .../aarch64/advsimd-intrinsics/vrndp.c | 8 + .../aarch64/advsimd-intrinsics/vrndx.c | 8 + .../aarch64/advsimd-intrinsics/vrsqrte.c | 91 +++++++++ .../aarch64/advsimd-intrinsics/vrsqrts.c | 97 +++++++++ .../aarch64/advsimd-intrinsics/vsub.c | 31 +++ 55 files changed, 2276 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op_float.inc create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/cmp_zero_op.inc create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqz_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgez_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtz_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclez_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltz_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtX.inc create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvta_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtm_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtp_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnm_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnm_1.c diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index bc9e798cc8f..8305520fbdd 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,101 @@ +2016-09-23 Matthew Wahab + + * gcc.target/advsimd-intrinsics/advsimd-intrinsics.exp: Enable + -march=armv8.2-a+fp16 when supported by the hardware. + * gcc.target/aarch64/advsimd-intrinsics/binary_op_float.inc: New. + * gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc: + Add F16 tests, enabled if macro HAS_FLOAT16_VARIANT is defined. Add + semi-colons to a macro invocations. + * gcc.target/aarch64/advsimd-intrinsics/cmp_fp_op.inc: Add F16 + tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is + defined. + * gcc.target/aarch64/advsimd-intrinsics/cmp_op.inc: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/cmp_zero_op.inc: New. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vabd.c: Add F16 + tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is + defined. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vabs.c: Likewise. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vadd.c: Likewise. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcage.c: Likewise. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcagt.c: Likewise. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcale.c: Likewise. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcalt.c: Likewise. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vceq.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vceqz_1.c: New. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcge.c: Add F16 + tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is + defined. + * gcc.target/aarch64/advsimd-intrinsics/vcgez_1.c: New. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcgt.c: Add F16 + tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is + defined. + * gcc.target/aarch64/advsimd-intrinsics/vcgtz_1.c: New. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcle.c: Add F16 + tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is + defined. + * gcc.target/aarch64/advsimd-intrinsics/vclez_1.c: New. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vclt.c: Add F16 + tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is + defined. + * gcc.target/aarch64/advsimd-intrinsics/vcltz_1.c: New. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcvt.c: Add F16 + tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is + defined. Also fix some white-space. + * gcc.target/aarch64/advsimd-intrinsics/vcvtX.inc: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvta_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtm_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtp_1.c: New. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vfma.c: Add F16 + tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is + defined. Also fix some long lines and white-space. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vfms.c: Add F16 + tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is + defined. Also fix some long lines and white-space. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vmax.c: Add F16 + tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is + defined. + * gcc.target/aarch64/advsimd-intrinsics/vmaxnm_1.c: New. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vmin.c: Add F16 + tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is + defined. + * gcc.target/aarch64/advsimd-intrinsics/vminnm_1.c: New. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vmul.c: Add F16 + tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is + defined. + * gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c: Likewise. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vmul_n.c: + Likewise. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vneg.c: + Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc: Likewise. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vpadd.c: + Likewise. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vpmax.c: + Likewise. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vpmin.c: + Likewise. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrecpe.c: + Likewise. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrecps.c: + Likewise. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrnd.c: + Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vrndX.inc: Likewise. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrnda.c: + Likewise. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrndm.c: + Likewise. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrndn.c: + Likewise. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrndp.c: + Likewise. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrndx.c: + Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c: Likewise. + * gcc.target/gcc.target/aarch64/advsimd-intrinsics/vsub.c: + Likewise. + 2016-09-23 Jiong Wang Matthew Wahab diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/advsimd-intrinsics.exp b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/advsimd-intrinsics.exp index ff399737c57..e93b8d5cd5a 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/advsimd-intrinsics.exp +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/advsimd-intrinsics.exp @@ -53,7 +53,10 @@ torture-init set-torture-options $C_TORTURE_OPTIONS {{}} $LTO_TORTURE_OPTIONS # Make sure Neon flags are provided, if necessary. Use fp16 if we can. -if {[check_effective_target_arm_neon_fp16_ok]} then { +# Use fp16 arithmetic operations if the hardware supports it. +if {[check_effective_target_arm_v8_2a_fp16_neon_hw]} then { + set additional_flags [add_options_for_arm_v8_2a_fp16_neon ""] +} elseif {[check_effective_target_arm_neon_fp16_ok]} then { set additional_flags [add_options_for_arm_neon_fp16 ""] } else { set additional_flags [add_options_for_arm_neon ""] diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op_float.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op_float.inc new file mode 100644 index 00000000000..cc1bfb3e7bf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op_float.inc @@ -0,0 +1,170 @@ +/* Floating-point only version of binary_op_no64.inc template. Currently only + float16_t is used. */ + +#include + +#define FNNAME1(NAME) exec_ ## NAME +#define FNNAME(NAME) FNNAME1(NAME) + +void FNNAME (INSN_NAME) (void) +{ + int i; + + /* Basic test: z = INSN (x, y), then store the result. */ +#define TEST_BINARY_OP1(INSN, Q, T1, T2, W, N) \ + VECT_VAR(vector_res, T1, W, N) = \ + INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N), \ + VECT_VAR(vector2, T1, W, N)); \ + vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N)) + +#define TEST_BINARY_OP(INSN, Q, T1, T2, W, N) \ + TEST_BINARY_OP1(INSN, Q, T1, T2, W, N) \ + +#ifdef HAS_FLOAT16_VARIANT + DECL_VARIABLE(vector, float, 16, 4); + DECL_VARIABLE(vector2, float, 16, 4); + DECL_VARIABLE(vector_res, float, 16, 4); + + DECL_VARIABLE(vector, float, 16, 8); + DECL_VARIABLE(vector2, float, 16, 8); + DECL_VARIABLE(vector_res, float, 16, 8); +#endif + +#ifdef HAS_FLOAT_VARIANT + DECL_VARIABLE(vector, float, 32, 2); + DECL_VARIABLE(vector2, float, 32, 2); + DECL_VARIABLE(vector_res, float, 32, 2); + + DECL_VARIABLE(vector, float, 32, 4); + DECL_VARIABLE(vector2, float, 32, 4); + DECL_VARIABLE(vector_res, float, 32, 4); +#endif + + clean_results (); + + /* Initialize input "vector" from "buffer". */ +#ifdef HAS_FLOAT16_VARIANT + VLOAD(vector, buffer, , float, f, 16, 4); + VLOAD(vector, buffer, q, float, f, 16, 8); +#endif +#ifdef HAS_FLOAT_VARIANT + VLOAD(vector, buffer, , float, f, 32, 2); + VLOAD(vector, buffer, q, float, f, 32, 4); +#endif + + /* Choose init value arbitrarily, will be used as comparison value. */ +#ifdef HAS_FLOAT16_VARIANT + VDUP(vector2, , float, f, 16, 4, -15.5f); + VDUP(vector2, q, float, f, 16, 8, -14.5f); +#endif +#ifdef HAS_FLOAT_VARIANT + VDUP(vector2, , float, f, 32, 2, -15.5f); + VDUP(vector2, q, float, f, 32, 4, -14.5f); +#endif + +#ifdef HAS_FLOAT16_VARIANT +#define FLOAT16_VARIANT(MACRO, VAR) \ + MACRO(VAR, , float, f, 16, 4); \ + MACRO(VAR, q, float, f, 16, 8); +#else +#define FLOAT16_VARIANT(MACRO, VAR) +#endif + +#ifdef HAS_FLOAT_VARIANT +#define FLOAT_VARIANT(MACRO, VAR) \ + MACRO(VAR, , float, f, 32, 2); \ + MACRO(VAR, q, float, f, 32, 4); +#else +#define FLOAT_VARIANT(MACRO, VAR) +#endif + +#define TEST_MACRO_NO64BIT_VARIANT_1_5(MACRO, VAR) \ + + /* Apply a binary operator named INSN_NAME. */ + FLOAT16_VARIANT(TEST_BINARY_OP, INSN_NAME); + FLOAT_VARIANT(TEST_BINARY_OP, INSN_NAME); + +#ifdef HAS_FLOAT16_VARIANT + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, ""); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, ""); + + /* Extra FP tests with special values (NaN, ....) */ + VDUP(vector, q, float, f, 16, 8, 1.0f); + VDUP(vector2, q, float, f, 16, 8, NAN); + TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_nan, + " FP special (NaN)"); + + VDUP(vector, q, float, f, 16, 8, -NAN); + VDUP(vector2, q, float, f, 16, 8, 1.0f); + TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_mnan, + " FP special (-NaN)"); + + VDUP(vector, q, float, f, 16, 8, 1.0f); + VDUP(vector2, q, float, f, 16, 8, HUGE_VALF); + TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_inf, + " FP special (inf)"); + + VDUP(vector, q, float, f, 16, 8, -HUGE_VALF); + VDUP(vector2, q, float, f, 16, 8, 1.0f); + TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_minf, + " FP special (-inf)"); + + VDUP(vector, q, float, f, 16, 8, 0.0f); + VDUP(vector2, q, float, f, 16, 8, -0.0f); + TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_zero1, + " FP special (-0.0)"); + + VDUP(vector, q, float, f, 16, 8, -0.0f); + VDUP(vector2, q, float, f, 16, 8, 0.0f); + TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_zero2, + " FP special (-0.0)"); +#endif + +#ifdef HAS_FLOAT_VARIANT + CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, ""); + CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, ""); + + /* Extra FP tests with special values (NaN, ....) */ + VDUP(vector, q, float, f, 32, 4, 1.0f); + VDUP(vector2, q, float, f, 32, 4, NAN); + TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4); + CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_nan, " FP special (NaN)"); + + VDUP(vector, q, float, f, 32, 4, -NAN); + VDUP(vector2, q, float, f, 32, 4, 1.0f); + TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4); + CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_mnan, " FP special (-NaN)"); + + VDUP(vector, q, float, f, 32, 4, 1.0f); + VDUP(vector2, q, float, f, 32, 4, HUGE_VALF); + TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4); + CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_inf, " FP special (inf)"); + + VDUP(vector, q, float, f, 32, 4, -HUGE_VALF); + VDUP(vector2, q, float, f, 32, 4, 1.0f); + TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4); + CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_minf, " FP special (-inf)"); + + VDUP(vector, q, float, f, 32, 4, 0.0f); + VDUP(vector2, q, float, f, 32, 4, -0.0f); + TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4); + CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_zero1, " FP special (-0.0)"); + + VDUP(vector, q, float, f, 32, 4, -0.0f); + VDUP(vector2, q, float, f, 32, 4, 0.0f); + TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4); + CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_zero2, " FP special (-0.0)"); +#endif +} + +int main (void) +{ + FNNAME (INSN_NAME) (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc index 1eb9271b7f5..a30f420e02f 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc @@ -28,6 +28,10 @@ void FNNAME (INSN_NAME) (void) /* Initialize input "vector" from "buffer". */ TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer); +#ifdef HAS_FLOAT16_VARIANT + VLOAD(vector, buffer, , float, f, 16, 4); + VLOAD(vector, buffer, q, float, f, 16, 8); +#endif #ifdef HAS_FLOAT_VARIANT VLOAD(vector, buffer, , float, f, 32, 2); VLOAD(vector, buffer, q, float, f, 32, 4); @@ -46,15 +50,27 @@ void FNNAME (INSN_NAME) (void) VDUP(vector2, q, uint, u, 8, 16, 0xf9); VDUP(vector2, q, uint, u, 16, 8, 0xfff2); VDUP(vector2, q, uint, u, 32, 4, 0xfffffff1); +#ifdef HAS_FLOAT16_VARIANT + VDUP(vector2, , float, f, 16, 4, -15.5f); + VDUP(vector2, q, float, f, 16, 8, -14.5f); +#endif #ifdef HAS_FLOAT_VARIANT VDUP(vector2, , float, f, 32, 2, -15.5f); VDUP(vector2, q, float, f, 32, 4, -14.5f); #endif +#ifdef HAS_FLOAT16_VARIANT +#define FLOAT16_VARIANT(MACRO, VAR) \ + MACRO(VAR, , float, f, 16, 4); \ + MACRO(VAR, q, float, f, 16, 8); +#else +#define FLOAT16_VARIANT(MACRO, VAR) +#endif + #ifdef HAS_FLOAT_VARIANT #define FLOAT_VARIANT(MACRO, VAR) \ MACRO(VAR, , float, f, 32, 2); \ - MACRO(VAR, q, float, f, 32, 4) + MACRO(VAR, q, float, f, 32, 4); #else #define FLOAT_VARIANT(MACRO, VAR) #endif @@ -72,7 +88,8 @@ void FNNAME (INSN_NAME) (void) MACRO(VAR, q, uint, u, 8, 16); \ MACRO(VAR, q, uint, u, 16, 8); \ MACRO(VAR, q, uint, u, 32, 4); \ - FLOAT_VARIANT(MACRO, VAR) + FLOAT_VARIANT(MACRO, VAR); \ + FLOAT16_VARIANT(MACRO, VAR); /* Apply a binary operator named INSN_NAME. */ TEST_MACRO_NO64BIT_VARIANT_1_5(TEST_BINARY_OP, INSN_NAME); @@ -90,6 +107,42 @@ void FNNAME (INSN_NAME) (void) CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, ""); CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, ""); +#ifdef HAS_FLOAT16_VARIANT + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, ""); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, ""); + + /* Extra FP tests with special values (NaN, ....) */ + VDUP(vector, q, float, f, 16, 8, 1.0f); + VDUP(vector2, q, float, f, 16, 8, NAN); + TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_nan, " FP special (NaN)"); + + VDUP(vector, q, float, f, 16, 8, -NAN); + VDUP(vector2, q, float, f, 16, 8, 1.0f); + TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_mnan, " FP special (-NaN)"); + + VDUP(vector, q, float, f, 16, 8, 1.0f); + VDUP(vector2, q, float, f, 16, 8, HUGE_VALF); + TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_inf, " FP special (inf)"); + + VDUP(vector, q, float, f, 16, 8, -HUGE_VALF); + VDUP(vector2, q, float, f, 16, 8, 1.0f); + TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_minf, " FP special (-inf)"); + + VDUP(vector, q, float, f, 16, 8, 0.0f); + VDUP(vector2, q, float, f, 16, 8, -0.0f); + TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_zero1, " FP special (-0.0)"); + + VDUP(vector, q, float, f, 16, 8, -0.0f); + VDUP(vector2, q, float, f, 16, 8, 0.0f); + TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_zero2, " FP special (-0.0)"); +#endif + #ifdef HAS_FLOAT_VARIANT CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, ""); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, ""); diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/cmp_fp_op.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/cmp_fp_op.inc index 33451d7e610..313badb2fb6 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/cmp_fp_op.inc +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/cmp_fp_op.inc @@ -15,6 +15,10 @@ each test file. */ extern ARRAY(expected2, uint, 32, 2); extern ARRAY(expected2, uint, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +extern ARRAY(expected2, uint, 16, 4); +extern ARRAY(expected2, uint, 16, 8); +#endif #define FNNAME1(NAME) exec_ ## NAME #define FNNAME(NAME) FNNAME1(NAME) @@ -37,17 +41,33 @@ void FNNAME (INSN_NAME) (void) DECL_VARIABLE(vector2, float, 32, 4); DECL_VARIABLE(vector_res, uint, 32, 2); DECL_VARIABLE(vector_res, uint, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector, float, 16, 4); + DECL_VARIABLE(vector, float, 16, 8); + DECL_VARIABLE(vector2, float, 16, 4); + DECL_VARIABLE(vector2, float, 16, 8); + DECL_VARIABLE(vector_res, uint, 16, 4); + DECL_VARIABLE(vector_res, uint, 16, 8); +#endif clean_results (); /* Initialize input "vector" from "buffer". */ VLOAD(vector, buffer, , float, f, 32, 2); VLOAD(vector, buffer, q, float, f, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VLOAD(vector, buffer, , float, f, 16, 4); + VLOAD(vector, buffer, q, float, f, 16, 8); +#endif /* Choose init value arbitrarily, will be used for vector comparison. */ VDUP(vector2, , float, f, 32, 2, -16.0f); VDUP(vector2, q, float, f, 32, 4, -14.0f); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector2, , float, f, 16, 4, -16.0f); + VDUP(vector2, q, float, f, 16, 8, -14.0f); +#endif /* Apply operator named INSN_NAME. */ TEST_VCOMP(INSN_NAME, , float, f, uint, 32, 2); @@ -56,15 +76,36 @@ void FNNAME (INSN_NAME) (void) TEST_VCOMP(INSN_NAME, q, float, f, uint, 32, 4); CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, ""); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VCOMP(INSN_NAME, , float, f, uint, 16, 4); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, ""); + + TEST_VCOMP(INSN_NAME, q, float, f, uint, 16, 8); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, ""); +#endif + /* Test again, with different input values. */ VDUP(vector2, , float, f, 32, 2, -10.0f); VDUP(vector2, q, float, f, 32, 4, 10.0f); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector2, , float, f, 16, 4, -10.0f); + VDUP(vector2, q, float, f, 16, 8, 10.0f); +#endif + TEST_VCOMP(INSN_NAME, , float, f, uint, 32, 2); CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected2, ""); TEST_VCOMP(INSN_NAME, q, float, f, uint, 32, 4); CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected2,""); + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VCOMP(INSN_NAME, , float, f, uint, 16, 4); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected2, ""); + + TEST_VCOMP(INSN_NAME, q, float, f, uint, 16, 8); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected2,""); +#endif } int main (void) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/cmp_op.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/cmp_op.inc index a09c5f5bb29..c8c5dfe83f9 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/cmp_op.inc +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/cmp_op.inc @@ -11,6 +11,17 @@ extern ARRAY(expected_uint, uint, 32, 2); extern ARRAY(expected_q_uint, uint, 8, 16); extern ARRAY(expected_q_uint, uint, 16, 8); extern ARRAY(expected_q_uint, uint, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +extern ARRAY(expected_float, uint, 16, 4); +extern ARRAY(expected_q_float, uint, 16, 8); +extern ARRAY(expected_nan, uint, 16, 4); +extern ARRAY(expected_mnan, uint, 16, 4); +extern ARRAY(expected_nan2, uint, 16, 4); +extern ARRAY(expected_inf, uint, 16, 4); +extern ARRAY(expected_minf, uint, 16, 4); +extern ARRAY(expected_inf2, uint, 16, 4); +extern ARRAY(expected_mzero, uint, 16, 4); +#endif extern ARRAY(expected_float, uint, 32, 2); extern ARRAY(expected_q_float, uint, 32, 4); extern ARRAY(expected_uint2, uint, 32, 2); @@ -48,6 +59,9 @@ void FNNAME (INSN_NAME) (void) DECL_VARIABLE(vector, uint, 8, 8); DECL_VARIABLE(vector, uint, 16, 4); DECL_VARIABLE(vector, uint, 32, 2); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE (vector, float, 16, 4); +#endif DECL_VARIABLE(vector, float, 32, 2); DECL_VARIABLE(vector, int, 8, 16); DECL_VARIABLE(vector, int, 16, 8); @@ -55,6 +69,9 @@ void FNNAME (INSN_NAME) (void) DECL_VARIABLE(vector, uint, 8, 16); DECL_VARIABLE(vector, uint, 16, 8); DECL_VARIABLE(vector, uint, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE (vector, float, 16, 8); +#endif DECL_VARIABLE(vector, float, 32, 4); DECL_VARIABLE(vector2, int, 8, 8); @@ -63,6 +80,9 @@ void FNNAME (INSN_NAME) (void) DECL_VARIABLE(vector2, uint, 8, 8); DECL_VARIABLE(vector2, uint, 16, 4); DECL_VARIABLE(vector2, uint, 32, 2); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE (vector2, float, 16, 4); +#endif DECL_VARIABLE(vector2, float, 32, 2); DECL_VARIABLE(vector2, int, 8, 16); DECL_VARIABLE(vector2, int, 16, 8); @@ -70,6 +90,9 @@ void FNNAME (INSN_NAME) (void) DECL_VARIABLE(vector2, uint, 8, 16); DECL_VARIABLE(vector2, uint, 16, 8); DECL_VARIABLE(vector2, uint, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE (vector2, float, 16, 8); +#endif DECL_VARIABLE(vector2, float, 32, 4); DECL_VARIABLE(vector_res, uint, 8, 8); @@ -88,6 +111,9 @@ void FNNAME (INSN_NAME) (void) VLOAD(vector, buffer, , uint, u, 8, 8); VLOAD(vector, buffer, , uint, u, 16, 4); VLOAD(vector, buffer, , uint, u, 32, 2); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VLOAD (vector, buffer, , float, f, 16, 4); +#endif VLOAD(vector, buffer, , float, f, 32, 2); VLOAD(vector, buffer, q, int, s, 8, 16); @@ -96,6 +122,9 @@ void FNNAME (INSN_NAME) (void) VLOAD(vector, buffer, q, uint, u, 8, 16); VLOAD(vector, buffer, q, uint, u, 16, 8); VLOAD(vector, buffer, q, uint, u, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VLOAD (vector, buffer, q, float, f, 16, 8); +#endif VLOAD(vector, buffer, q, float, f, 32, 4); /* Choose init value arbitrarily, will be used for vector @@ -106,6 +135,9 @@ void FNNAME (INSN_NAME) (void) VDUP(vector2, , uint, u, 8, 8, 0xF3); VDUP(vector2, , uint, u, 16, 4, 0xFFF2); VDUP(vector2, , uint, u, 32, 2, 0xFFFFFFF1); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP (vector2, , float, f, 16, 4, -15.0f); +#endif VDUP(vector2, , float, f, 32, 2, -15.0f); VDUP(vector2, q, int, s, 8, 16, -4); @@ -114,6 +146,9 @@ void FNNAME (INSN_NAME) (void) VDUP(vector2, q, uint, u, 8, 16, 0xF4); VDUP(vector2, q, uint, u, 16, 8, 0xFFF6); VDUP(vector2, q, uint, u, 32, 4, 0xFFFFFFF2); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP (vector2, q, float, f, 16, 8, -14.0f); +#endif VDUP(vector2, q, float, f, 32, 4, -14.0f); /* The comparison operators produce only unsigned results, which @@ -154,9 +189,17 @@ void FNNAME (INSN_NAME) (void) CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_q_uint, ""); /* The float variants. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4); + CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_float, ""); +#endif TEST_VCOMP(INSN_NAME, , float, f, uint, 32, 2); CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_float, ""); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VCOMP (INSN_NAME, q, float, f, uint, 16, 8); + CHECK (TEST_MSG, uint, 16, 8, PRIx16, expected_q_float, ""); +#endif TEST_VCOMP(INSN_NAME, q, float, f, uint, 32, 4); CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_q_float, ""); @@ -176,6 +219,43 @@ void FNNAME (INSN_NAME) (void) /* Extra FP tests with special values (NaN, ....). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP (vector, , float, f, 16, 4, 1.0); + VDUP (vector2, , float, f, 16, 4, NAN); + TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4); + CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_nan, "FP special (NaN)"); + + VDUP (vector, , float, f, 16, 4, 1.0); + VDUP (vector2, , float, f, 16, 4, -NAN); + TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4); + CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_mnan, " FP special (-NaN)"); + + VDUP (vector, , float, f, 16, 4, NAN); + VDUP (vector2, , float, f, 16, 4, 1.0); + TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4); + CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_nan2, " FP special (NaN)"); + + VDUP (vector, , float, f, 16, 4, 1.0); + VDUP (vector2, , float, f, 16, 4, HUGE_VALF); + TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4); + CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_inf, " FP special (inf)"); + + VDUP (vector, , float, f, 16, 4, 1.0); + VDUP (vector2, , float, f, 16, 4, -HUGE_VALF); + TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4); + CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_minf, " FP special (-inf)"); + + VDUP (vector, , float, f, 16, 4, HUGE_VALF); + VDUP (vector2, , float, f, 16, 4, 1.0); + TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4); + CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_inf2, " FP special (inf)"); + + VDUP (vector, , float, f, 16, 4, -0.0); + VDUP (vector2, , float, f, 16, 4, 0.0); + TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4); + CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_mzero, " FP special (-0.0)"); +#endif + VDUP(vector, , float, f, 32, 2, 1.0); VDUP(vector2, , float, f, 32, 2, NAN); TEST_VCOMP(INSN_NAME, , float, f, uint, 32, 2); diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/cmp_zero_op.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/cmp_zero_op.inc new file mode 100644 index 00000000000..610272f8c15 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/cmp_zero_op.inc @@ -0,0 +1,111 @@ +/* Template file for the validation of compare against zero operators. + + This file is base on cmp_op.inc. It is meant to be included by the relevant + test files, which have to define the intrinsic family to test. If a given + intrinsic supports variants which are not supported by all the other + operators, these can be tested by providing a definition for EXTRA_TESTS. */ + +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" +#include + +/* Additional expected results declaration, they are initialized in + each test file. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +extern ARRAY(expected_float, uint, 16, 4); +extern ARRAY(expected_q_float, uint, 16, 8); +extern ARRAY(expected_uint2, uint, 16, 4); +extern ARRAY(expected_uint3, uint, 16, 4); +extern ARRAY(expected_uint4, uint, 16, 4); +extern ARRAY(expected_nan, uint, 16, 4); +extern ARRAY(expected_mnan, uint, 16, 4); +extern ARRAY(expected_inf, uint, 16, 4); +extern ARRAY(expected_minf, uint, 16, 4); +extern ARRAY(expected_zero, uint, 16, 4); +extern ARRAY(expected_mzero, uint, 16, 4); +#endif + +#define FNNAME1(NAME) exec_ ## NAME +#define FNNAME(NAME) FNNAME1(NAME) + +void FNNAME (INSN_NAME) (void) +{ + /* Basic test: y=vcomp(x1,x2), then store the result. */ +#define TEST_VCOMP1(INSN, Q, T1, T2, T3, W, N) \ + VECT_VAR(vector_res, T3, W, N) = \ + INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N)); \ + vst1##Q##_u##W(VECT_VAR(result, T3, W, N), VECT_VAR(vector_res, T3, W, N)) + +#define TEST_VCOMP(INSN, Q, T1, T2, T3, W, N) \ + TEST_VCOMP1(INSN, Q, T1, T2, T3, W, N) + + /* No need for 64 bits elements. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE (vector, float, 16, 4); + DECL_VARIABLE (vector, float, 16, 8); +#endif + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector_res, uint, 16, 4); + DECL_VARIABLE(vector_res, uint, 16, 8); +#endif + + clean_results (); + + /* Choose init value arbitrarily, will be used for vector + comparison. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP (vector, , float, f, 16, 4, -15.0f); + VDUP (vector, q, float, f, 16, 8, 14.0f); +#endif + + /* Float variants. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4); + TEST_VCOMP (INSN_NAME, q, float, f, uint, 16, 8); +#endif + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_float, ""); + CHECK (TEST_MSG, uint, 16, 8, PRIx16, expected_q_float, ""); +#endif + + /* Extra FP tests with special values (NaN, ....). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP (vector, , float, f, 16, 4, NAN); + TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4); + CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_nan, "FP special (NaN)"); + + VDUP (vector, , float, f, 16, 4, -NAN); + TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4); + CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_mnan, " FP special (-NaN)"); + + VDUP (vector, , float, f, 16, 4, HUGE_VALF); + TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4); + CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_inf, " FP special (inf)"); + + VDUP (vector, , float, f, 16, 4, -HUGE_VALF); + TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4); + CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_minf, " FP special (-inf)"); + + VDUP (vector, , float, f, 16, 4, 0.0); + TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4); + CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_zero, " FP special (0.0)"); + + VDUP (vector, , float, f, 16, 4, 0.0); + TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4); + CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_mzero, " FP special (-0.0)"); +#endif + +#ifdef EXTRA_TESTS + EXTRA_TESTS(); +#endif +} + +int main (void) +{ + FNNAME (INSN_NAME) (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabd.c index 67d2af144d5..30490653a18 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabd.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabd.c @@ -30,10 +30,20 @@ VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffd0, 0xffffffd1, 0xffffffd2, 0xffffffd3 }; VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x42407ae1, 0x423c7ae1, 0x42387ae1, 0x42347ae1 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0x4e13, 0x4dd3, + 0x4d93, 0x4d53 }; +VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0x5204, 0x51e4, 0x51c4, 0x51a4, + 0x5184, 0x5164, 0x5144, 0x5124 }; +#endif /* Additional expected results for float32 variants with specially chosen input values. */ VECT_VAR_DECL(expected_float32,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_float16, hfloat, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0 }; +#endif #define TEST_MSG "VABD/VABDQ" void exec_vabd (void) @@ -65,6 +75,17 @@ void exec_vabd (void) DECL_VABD_VAR(vector2); DECL_VABD_VAR(vector_res); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector1, float, 16, 4); + DECL_VARIABLE(vector1, float, 16, 8); + + DECL_VARIABLE(vector2, float, 16, 4); + DECL_VARIABLE(vector2, float, 16, 8); + + DECL_VARIABLE(vector_res, float, 16, 4); + DECL_VARIABLE(vector_res, float, 16, 8); +#endif + clean_results (); /* Initialize input "vector1" from "buffer". */ @@ -82,6 +103,12 @@ void exec_vabd (void) VLOAD(vector1, buffer, q, uint, u, 16, 8); VLOAD(vector1, buffer, q, uint, u, 32, 4); VLOAD(vector1, buffer, q, float, f, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VLOAD(vector1, buffer, , float, f, 16, 4); + VLOAD(vector1, buffer, , float, f, 16, 4); + VLOAD(vector1, buffer, q, float, f, 16, 8); + VLOAD(vector1, buffer, q, float, f, 16, 8); +#endif /* Choose init value arbitrarily. */ VDUP(vector2, , int, s, 8, 8, 1); @@ -98,6 +125,10 @@ void exec_vabd (void) VDUP(vector2, q, uint, u, 16, 8, 12); VDUP(vector2, q, uint, u, 32, 4, 32); VDUP(vector2, q, float, f, 32, 4, 32.12f); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector2, , float, f, 16, 4, 8.3f); + VDUP(vector2, q, float, f, 16, 8, 32.12f); +#endif /* Execute the tests. */ TEST_VABD(, int, s, 8, 8); @@ -115,6 +146,11 @@ void exec_vabd (void) TEST_VABD(q, uint, u, 32, 4); TEST_VABD(q, float, f, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VABD(, float, f, 16, 4); + TEST_VABD(q, float, f, 16, 8); +#endif + CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, ""); CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, ""); CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, ""); @@ -129,7 +165,10 @@ void exec_vabd (void) CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, ""); CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, ""); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, ""); - +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, ""); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, ""); +#endif /* Extra FP tests with special values (-0.0, ....) */ VDUP(vector1, q, float, f, 32, 4, -0.0f); @@ -137,11 +176,27 @@ void exec_vabd (void) TEST_VABD(q, float, f, 32, 4); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_float32, " FP special (-0.0)"); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector1, q, float, f, 16, 8, -0.0f); + VDUP(vector2, q, float, f, 16, 8, 0.0); + TEST_VABD(q, float, f, 16, 8); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_float16, + " FP special (-0.0)"); +#endif + /* Extra FP tests with special values (-0.0, ....) */ VDUP(vector1, q, float, f, 32, 4, 0.0f); VDUP(vector2, q, float, f, 32, 4, -0.0); TEST_VABD(q, float, f, 32, 4); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_float32, " FP special (-0.0)"); + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector1, q, float, f, 16, 8, 0.0f); + VDUP(vector2, q, float, f, 16, 8, -0.0); + TEST_VABD(q, float, f, 16, 8); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_float16, + " FP special (-0.0)"); +#endif } int main (void) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabs.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabs.c index 9c80ef1fca2..9d6d5b21cf4 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabs.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabs.c @@ -21,24 +21,52 @@ VECT_VAR_DECL(expected,int,32,4) [] = { 0x10, 0xf, 0xe, 0xd }; /* Expected results for float32 variants. Needs to be separated since the generic test function does not test floating-point versions. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_float16, hfloat, 16, 4) [] = { 0x409a, 0x409a, + 0x409a, 0x409a }; +VECT_VAR_DECL(expected_float16, hfloat, 16, 8) [] = { 0x42cd, 0x42cd, + 0x42cd, 0x42cd, + 0x42cd, 0x42cd, + 0x42cd, 0x42cd }; +#endif VECT_VAR_DECL(expected_float32,hfloat,32,2) [] = { 0x40133333, 0x40133333 }; VECT_VAR_DECL(expected_float32,hfloat,32,4) [] = { 0x4059999a, 0x4059999a, 0x4059999a, 0x4059999a }; void exec_vabs_f32(void) { +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector, float, 16, 4); + DECL_VARIABLE(vector, float, 16, 8); +#endif DECL_VARIABLE(vector, float, 32, 2); DECL_VARIABLE(vector, float, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector_res, float, 16, 4); + DECL_VARIABLE(vector_res, float, 16, 8); +#endif DECL_VARIABLE(vector_res, float, 32, 2); DECL_VARIABLE(vector_res, float, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector, , float, f, 16, 4, -2.3f); + VDUP(vector, q, float, f, 16, 8, 3.4f); +#endif VDUP(vector, , float, f, 32, 2, -2.3f); VDUP(vector, q, float, f, 32, 4, 3.4f); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_UNARY_OP(INSN_NAME, , float, f, 16, 4); + TEST_UNARY_OP(INSN_NAME, q, float, f, 16, 8); +#endif TEST_UNARY_OP(INSN_NAME, , float, f, 32, 2); TEST_UNARY_OP(INSN_NAME, q, float, f, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_float16, ""); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_float16, ""); +#endif CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_float32, ""); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_float32, ""); } diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vadd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vadd.c index 7be14016f42..1561dc1c262 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vadd.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vadd.c @@ -43,6 +43,14 @@ VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff3, VECT_VAR_DECL(expected_float32,hfloat,32,2) [] = { 0x40d9999a, 0x40d9999a }; VECT_VAR_DECL(expected_float32,hfloat,32,4) [] = { 0x41100000, 0x41100000, 0x41100000, 0x41100000 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_float16, hfloat, 16, 4) [] = { 0x46cd, 0x46cd, + 0x46cd, 0x46cd }; +VECT_VAR_DECL(expected_float16, hfloat, 16, 8) [] = { 0x4880, 0x4880, + 0x4880, 0x4880, + 0x4880, 0x4880, + 0x4880, 0x4880 }; +#endif void exec_vadd_f32(void) { @@ -66,4 +74,27 @@ void exec_vadd_f32(void) CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_float32, ""); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_float32, ""); + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector, float, 16, 4); + DECL_VARIABLE(vector, float, 16, 8); + + DECL_VARIABLE(vector2, float, 16, 4); + DECL_VARIABLE(vector2, float, 16, 8); + + DECL_VARIABLE(vector_res, float, 16, 4); + DECL_VARIABLE(vector_res, float, 16, 8); + + VDUP(vector, , float, f, 16, 4, 2.3f); + VDUP(vector, q, float, f, 16, 8, 3.4f); + + VDUP(vector2, , float, f, 16, 4, 4.5f); + VDUP(vector2, q, float, f, 16, 8, 5.6f); + + TEST_BINARY_OP(INSN_NAME, , float, f, 16, 4); + TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8); + + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_float16, ""); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_float16, ""); +#endif } diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcage.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcage.c index 1fadf6644a5..ab00b961ef4 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcage.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcage.c @@ -11,3 +11,13 @@ VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffff, 0xffffffff, VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xffffffff, 0xffffffff }; VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }; + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected, uint, 16, 4) [] = { 0xffff, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected, uint, 16, 8) [] = { 0xffff, 0xffff, 0xffff, 0x0, + 0x0, 0x0, 0x0, 0x0 }; + +VECT_VAR_DECL (expected2, uint, 16, 4) [] = { 0xffff, 0xffff, 0xffff, 0xffff }; +VECT_VAR_DECL (expected2, uint, 16, 8) [] = { 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0x0 }; +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagt.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagt.c index b1144a20bdb..81c46a64840 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagt.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagt.c @@ -11,3 +11,13 @@ VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffff, 0xffffffff, VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xffffffff, 0xffffffff }; VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }; + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected, uint, 16, 8) [] = { 0xffff, 0xffff, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0 }; + +VECT_VAR_DECL (expected2, uint, 16, 4) [] = { 0xffff, 0xffff, 0xffff, 0xffff }; +VECT_VAR_DECL (expected2, uint, 16, 8) [] = { 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0x0, 0x0 }; +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcale.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcale.c index bff9e4a1a33..091ffaf6b83 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcale.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcale.c @@ -9,3 +9,13 @@ VECT_VAR_DECL(expected,uint,32,4) [] = { 0x0, 0x0, 0xffffffff, 0xffffffff }; VECT_VAR_DECL(expected2,uint,32,2) [] = { 0x0, 0x0 }; VECT_VAR_DECL(expected2,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 }; + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected, uint, 16, 4) [] = { 0xffff, 0xffff, 0xffff, 0xffff }; +VECT_VAR_DECL (expected, uint, 16, 8) [] = { 0x0, 0x0, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff }; + +VECT_VAR_DECL (expected2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected2, uint, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xffff, 0xffff }; +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalt.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalt.c index ed652ebeb3f..525176afa0e 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalt.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalt.c @@ -9,3 +9,13 @@ VECT_VAR_DECL(expected,uint,32,4) [] = { 0x0, 0x0, 0x0, 0xffffffff }; VECT_VAR_DECL(expected2,uint,32,2) [] = { 0x0, 0x0 }; VECT_VAR_DECL(expected2,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 }; + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected, uint, 16, 4) [] = { 0x0, 0xffff, 0xffff, 0xffff }; +VECT_VAR_DECL (expected, uint, 16, 8) [] = { 0x0, 0x0, 0x0, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff }; + +VECT_VAR_DECL (expected2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected2, uint, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xffff }; +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceq.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceq.c index 1e21d50402f..ede01fb1afa 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceq.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceq.c @@ -32,6 +32,12 @@ VECT_VAR_DECL(expected_q_uint,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffff, 0x0 }; VECT_VAR_DECL(expected_q_uint,uint,32,4) [] = { 0x0, 0x0, 0xffffffff, 0x0 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0x0, 0xffff, 0x0, 0x0 }; +VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0x0, 0x0, 0xffff, 0x0, + 0x0, 0x0, 0x0, 0x0, }; +#endif + VECT_VAR_DECL(expected_float,uint,32,2) [] = { 0x0, 0xffffffff }; VECT_VAR_DECL(expected_q_float,uint,32,4) [] = { 0x0, 0x0, 0xffffffff, 0x0 }; @@ -39,6 +45,18 @@ VECT_VAR_DECL(expected_uint2,uint,32,2) [] = { 0xffffffff, 0x0 }; VECT_VAR_DECL(expected_uint3,uint,32,2) [] = { 0x0, 0xffffffff }; VECT_VAR_DECL(expected_uint4,uint,32,2) [] = { 0xffffffff, 0x0 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_nan2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; + +VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_inf2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0xffff, 0xffff, + 0xffff, 0xffff }; +#endif + VECT_VAR_DECL(expected_nan,uint,32,2) [] = { 0x0, 0x0 }; VECT_VAR_DECL(expected_mnan,uint,32,2) [] = { 0x0, 0x0 }; VECT_VAR_DECL(expected_nan2,uint,32,2) [] = { 0x0, 0x0 }; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqz_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqz_1.c new file mode 100644 index 00000000000..eefaa7acfb5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqz_1.c @@ -0,0 +1,27 @@ +/* This file tests an intrinsic which currently has only an f16 variant and that + is only available when FP16 arithmetic instructions are supported. */ +/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ + +#define INSN_NAME vceqz +#define TEST_MSG "VCEQZ/VCEQZQ" + +#include "cmp_zero_op.inc" + +/* Expected results. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0 }; +#endif + +/* Extra FP tests with special values (NaN, ....). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0xffff, 0xffff, + 0xffff, 0xffff }; +VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0xffff, 0xffff, + 0xffff, 0xffff }; +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcge.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcge.c index 22a5d67bfa7..0ec7c7b07a4 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcge.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcge.c @@ -28,6 +28,14 @@ VECT_VAR_DECL(expected_q_uint,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0, 0, 0x0, 0xffff, 0xffff }; VECT_VAR_DECL(expected_q_uint,uint,32,4) [] = { 0x0, 0x0, 0xffffffff, 0xffffffff }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0x0, 0xffff, 0xffff, 0xffff }; +VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0x0, 0x0, + 0xffff, 0xffff, + 0xffff, 0xffff, + 0xffff, 0xffff }; +#endif + VECT_VAR_DECL(expected_float,uint,32,2) [] = { 0x0, 0xffffffff }; VECT_VAR_DECL(expected_q_float,uint,32,4) [] = { 0x0, 0x0, 0xffffffff, 0xffffffff }; @@ -35,6 +43,20 @@ VECT_VAR_DECL(expected_uint2,uint,32,2) [] = { 0xffffffff, 0xffffffff }; VECT_VAR_DECL(expected_uint3,uint,32,2) [] = { 0x0, 0xffffffff }; VECT_VAR_DECL(expected_uint4,uint,32,2) [] = { 0xffffffff, 0xffffffff }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_nan2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; + +VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0xffff, 0xffff, + 0xffff, 0xffff }; +VECT_VAR_DECL (expected_inf2, uint, 16, 4) [] = { 0xffff, 0xffff, + 0xffff, 0xffff }; +VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0xffff, 0xffff, + 0xffff, 0xffff }; +#endif + VECT_VAR_DECL(expected_nan,uint,32,2) [] = { 0x0, 0x0 }; VECT_VAR_DECL(expected_mnan,uint,32,2) [] = { 0x0, 0x0 }; VECT_VAR_DECL(expected_nan2,uint,32,2) [] = { 0x0, 0x0 }; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgez_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgez_1.c new file mode 100644 index 00000000000..3ce74f26a9c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgez_1.c @@ -0,0 +1,30 @@ +/* This file tests an intrinsic which currently has only an f16 variant and that + is only available when FP16 arithmetic instructions are supported. */ +/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ + +#define INSN_NAME vcgez +#define TEST_MSG "VCGEZ/VCGEZQ" + +#include "cmp_zero_op.inc" + +/* Expected results. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0xffff, 0xffff, + 0xffff, 0xffff, + 0xffff, 0xffff, + 0xffff, 0xffff }; +#endif + +/* Extra FP tests with special values (NaN, ....). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0xffff, 0xffff, + 0xffff, 0xffff }; +VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0xffff, 0xffff, + 0xffff, 0xffff }; +VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0xffff, 0xffff, + 0xffff, 0xffff }; +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgt.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgt.c index c44819a0d16..3976d57202d 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgt.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgt.c @@ -28,6 +28,14 @@ VECT_VAR_DECL(expected_q_uint,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffff }; VECT_VAR_DECL(expected_q_uint,uint,32,4) [] = { 0x0, 0x0, 0x0, 0xffffffff }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0x0, 0x0, 0xffff, 0xffff }; +VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0x0, 0x0, + 0x0, 0xffff, + 0xffff, 0xffff, + 0xffff, 0xffff }; +#endif + VECT_VAR_DECL(expected_float,uint,32,2) [] = { 0x0, 0x0 }; VECT_VAR_DECL(expected_q_float,uint,32,4) [] = { 0x0, 0x0, 0x0, 0xffffffff }; @@ -35,6 +43,19 @@ VECT_VAR_DECL(expected_uint2,uint,32,2) [] = { 0x0, 0xffffffff }; VECT_VAR_DECL(expected_uint3,uint,32,2) [] = { 0x0, 0x0 }; VECT_VAR_DECL(expected_uint4,uint,32,2) [] = { 0x0, 0xffffffff }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_nan2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; + +VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0xffff, 0xffff, + 0xffff, 0xffff }; +VECT_VAR_DECL (expected_inf2, uint, 16, 4) [] = { 0xffff, 0xffff, + 0xffff, 0xffff }; +VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +#endif + VECT_VAR_DECL(expected_nan,uint,32,2) [] = { 0x0, 0x0 }; VECT_VAR_DECL(expected_mnan,uint,32,2) [] = { 0x0, 0x0 }; VECT_VAR_DECL(expected_nan2,uint,32,2) [] = { 0x0, 0x0 }; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtz_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtz_1.c new file mode 100644 index 00000000000..a096dc793f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtz_1.c @@ -0,0 +1,28 @@ +/* This file tests an intrinsic which currently has only an f16 variant and that + is only available when FP16 arithmetic instructions are supported. */ +/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ + +#define INSN_NAME vcgtz +#define TEST_MSG "VCGTZ/VCGTZQ" + +#include "cmp_zero_op.inc" + +/* Expected results. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0xffff, 0xffff, + 0xffff, 0xffff, + 0xffff, 0xffff, + 0xffff, 0xffff }; +#endif + +/* Extra FP tests with special values (NaN, ....). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0xffff, 0xffff, + 0xffff, 0xffff }; +VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcle.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcle.c index a59b5432801..49f89d80063 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcle.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcle.c @@ -31,6 +31,14 @@ VECT_VAR_DECL(expected_q_uint,uint,16,8) [] = { 0xffff, 0xffff, 0xffff, 0xffff, VECT_VAR_DECL(expected_q_uint,uint,32,4) [] = { 0xffffffff, 0xffffffff, 0xffffffff, 0x0 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0xffff, 0xffff, 0x0, 0x0 }; +VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0xffff, 0xffff, + 0xffff, 0x0, + 0x0, 0x0, + 0x0, 0x0 }; +#endif + VECT_VAR_DECL(expected_float,uint,32,2) [] = { 0xffffffff, 0xffffffff }; VECT_VAR_DECL(expected_q_float,uint,32,4) [] = { 0xffffffff, 0xffffffff, 0xffffffff, 0x0 }; @@ -39,6 +47,20 @@ VECT_VAR_DECL(expected_uint2,uint,32,2) [] = { 0xffffffff, 0x0 }; VECT_VAR_DECL(expected_uint3,uint,32,2) [] = { 0xffffffff, 0xffffffff }; VECT_VAR_DECL(expected_uint4,uint,32,2) [] = { 0xffffffff, 0x0 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_nan2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; + +VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0xffff, 0xffff, + 0xffff, 0xffff }; +VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_inf2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; + +VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0xffff, 0xffff, + 0xffff, 0xffff }; +#endif + VECT_VAR_DECL(expected_nan,uint,32,2) [] = { 0x0, 0x0 }; VECT_VAR_DECL(expected_mnan,uint,32,2) [] = { 0x0, 0x0 }; VECT_VAR_DECL(expected_nan2,uint,32,2) [] = { 0x0, 0x0 }; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclez_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclez_1.c new file mode 100644 index 00000000000..7e18e3d3b72 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclez_1.c @@ -0,0 +1,29 @@ +/* This file tests an intrinsic which currently has only an f16 variant and that + is only available when FP16 arithmetic instructions are supported. */ +/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ + +#define INSN_NAME vclez +#define TEST_MSG "VCLEZ/VCLEZQ" + +#include "cmp_zero_op.inc" + +/* Expected results. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0xffff, 0xffff, + 0xffff, 0xffff }; +VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0 }; +#endif + +/* Extra FP tests with special values (NaN, ....). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; + +VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0xffff, 0xffff, + 0xffff, 0xffff }; +VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0xffff, 0xffff, + 0xffff, 0xffff }; +VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0xffff, 0xffff, + 0xffff, 0xffff }; +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclt.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclt.c index 6ef2b4c6ed3..b6f8d872dae 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclt.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclt.c @@ -30,6 +30,14 @@ VECT_VAR_DECL(expected_q_uint,uint,16,8) [] = { 0xffff, 0xffff, 0xffff, 0xffff, VECT_VAR_DECL(expected_q_uint,uint,32,4) [] = { 0xffffffff, 0xffffffff, 0x0, 0x0 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0xffff, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0xffff, 0xffff, + 0x0, 0x0, + 0x0, 0x0, + 0x0, 0x0 }; +#endif + VECT_VAR_DECL(expected_float,uint,32,2) [] = { 0xffffffff, 0x0 }; VECT_VAR_DECL(expected_q_float,uint,32,4) [] = { 0xffffffff, 0xffffffff, 0x0, 0x0 }; @@ -38,6 +46,19 @@ VECT_VAR_DECL(expected_uint2,uint,32,2) [] = { 0x0, 0x0 }; VECT_VAR_DECL(expected_uint3,uint,32,2) [] = { 0xffffffff, 0x0 }; VECT_VAR_DECL(expected_uint4,uint,32,2) [] = { 0x0, 0x0 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_nan2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; + +VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0xffff, 0xffff, + 0xffff, 0xffff }; +VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_inf2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; + +VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +#endif + VECT_VAR_DECL(expected_nan,uint,32,2) [] = { 0x0, 0x0 }; VECT_VAR_DECL(expected_mnan,uint,32,2) [] = { 0x0, 0x0 }; VECT_VAR_DECL(expected_nan2,uint,32,2) [] = { 0x0, 0x0 }; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltz_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltz_1.c new file mode 100644 index 00000000000..9b75cc7973d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltz_1.c @@ -0,0 +1,27 @@ +/* This file tests an intrinsic which currently has only an f16 variant and that + is only available when FP16 arithmetic instructions are supported. */ +/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ + +#define INSN_NAME vcltz +#define TEST_MSG "VCLTZ/VCLTZQ" + +#include "cmp_zero_op.inc" + +/* Expected results. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0xffff, 0xffff, + 0xffff, 0xffff }; +VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0 }; +#endif + +/* Extra FP tests with special values (NaN, ....). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; + +VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0xffff, 0xffff, + 0xffff, 0xffff }; +VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt.c index 8e80f1e0e98..b2b861af8e4 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt.c @@ -4,36 +4,99 @@ #include /* Expected results for vcvt. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_s, hfloat, 16, 4) [] = +{ 0xcc00, 0xcb80, 0xcb00, 0xca80 }; +VECT_VAR_DECL(expected_u, hfloat, 16, 4) [] = +{ 0x7c00, 0x7c00, 0x7c00, 0x7c00, }; +VECT_VAR_DECL(expected_s, hfloat, 16, 8) [] = +{ 0xcc00, 0xcb80, 0xcb00, 0xca80, + 0xca00, 0xc980, 0xc900, 0xc880 }; +VECT_VAR_DECL(expected_u, hfloat, 16, 8) [] = +{ 0x7c00, 0x7c00, 0x7c00, 0x7c00, + 0x7c00, 0x7c00, 0x7c00, 0x7c00, }; +#endif VECT_VAR_DECL(expected_s,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 }; VECT_VAR_DECL(expected_u,hfloat,32,2) [] = { 0x4f800000, 0x4f800000 }; VECT_VAR_DECL(expected_s,hfloat,32,4) [] = { 0xc1800000, 0xc1700000, - 0xc1600000, 0xc1500000 }; + 0xc1600000, 0xc1500000 }; VECT_VAR_DECL(expected_u,hfloat,32,4) [] = { 0x4f800000, 0x4f800000, - 0x4f800000, 0x4f800000 }; + 0x4f800000, 0x4f800000 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected, int, 16, 4) [] = { 0xfff1, 0x5, 0xfff1, 0x5 }; +VECT_VAR_DECL(expected, uint, 16, 4) [] = { 0x0, 0x5, 0x0, 0x5 }; +VECT_VAR_DECL(expected, int, 16, 8) [] = { 0x0, 0x0, 0xf, 0xfff1, + 0x0, 0x0, 0xf, 0xfff1 }; +VECT_VAR_DECL(expected, uint, 16, 8) [] = { 0x0, 0x0, 0xf, 0x0, + 0x0, 0x0, 0xf, 0x0 }; +#endif VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff1, 0x5 }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0x0, 0x5 }; VECT_VAR_DECL(expected,int,32,4) [] = { 0x0, 0x0, 0xf, 0xfffffff1 }; VECT_VAR_DECL(expected,uint,32,4) [] = { 0x0, 0x0, 0xf, 0x0 }; /* Expected results for vcvt_n. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_vcvt_n_s, hfloat, 16, 4) [] = { 0xc400, 0xc380, + 0xc300, 0xc280 }; +VECT_VAR_DECL(expected_vcvt_n_u, hfloat, 16, 4) [] = { 0x6000, 0x6000, + 0x6000, 0x6000 }; +VECT_VAR_DECL(expected_vcvt_n_s, hfloat, 16, 8) [] = { 0xb000, 0xaf80, + 0xaf00, 0xae80, + 0xae00, 0xad80, + 0xad00, 0xac80 }; +VECT_VAR_DECL(expected_vcvt_n_u, hfloat, 16, 8) [] = { 0x4c00, 0x4c00, + 0x4c00, 0x4c00, + 0x4c00, 0x4c00, + 0x4c00, 0x4c00 }; +#endif VECT_VAR_DECL(expected_vcvt_n_s,hfloat,32,2) [] = { 0xc0800000, 0xc0700000 }; VECT_VAR_DECL(expected_vcvt_n_u,hfloat,32,2) [] = { 0x4c000000, 0x4c000000 }; VECT_VAR_DECL(expected_vcvt_n_s,hfloat,32,4) [] = { 0xb2800000, 0xb2700000, 0xb2600000, 0xb2500000 }; VECT_VAR_DECL(expected_vcvt_n_u,hfloat,32,4) [] = { 0x49800000, 0x49800000, 0x49800000, 0x49800000 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_vcvt_n, int, 16, 4) [] = { 0xffc3, 0x15, + 0xffc3, 0x15 }; +VECT_VAR_DECL(expected_vcvt_n, uint, 16, 4) [] = { 0x0, 0x2a6, 0x0, 0x2a6 }; +VECT_VAR_DECL(expected_vcvt_n, int, 16, 8) [] = { 0x0, 0x0, 0x78f, 0xf871, + 0x0, 0x0, 0x78f, 0xf871 }; +VECT_VAR_DECL(expected_vcvt_n, uint, 16, 8) [] = { 0x0, 0x0, 0xf1e0, 0x0, + 0x0, 0x0, 0xf1e0, 0x0 }; +#endif VECT_VAR_DECL(expected_vcvt_n,int,32,2) [] = { 0xff0b3333, 0x54cccd }; VECT_VAR_DECL(expected_vcvt_n,uint,32,2) [] = { 0x0, 0x15 }; VECT_VAR_DECL(expected_vcvt_n,int,32,4) [] = { 0x0, 0x0, 0x1e3d7, 0xfffe1c29 }; VECT_VAR_DECL(expected_vcvt_n,uint,32,4) [] = { 0x0, 0x0, 0x1e, 0x0 }; /* Expected results for vcvt with rounding. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_rounding, int, 16, 4) [] = { 0xa, 0xa, 0xa, 0xa }; +VECT_VAR_DECL(expected_rounding, uint, 16, 4) [] = { 0xa, 0xa, 0xa, 0xa }; +VECT_VAR_DECL(expected_rounding, int, 16, 8) [] = { 0x7d, 0x7d, 0x7d, 0x7d, + 0x7d, 0x7d, 0x7d, 0x7d }; +VECT_VAR_DECL(expected_rounding, uint, 16, 8) [] = { 0x7d, 0x7d, 0x7d, 0x7d, + 0x7d, 0x7d, 0x7d, 0x7d }; +#endif VECT_VAR_DECL(expected_rounding,int,32,2) [] = { 0xa, 0xa }; VECT_VAR_DECL(expected_rounding,uint,32,2) [] = { 0xa, 0xa }; VECT_VAR_DECL(expected_rounding,int,32,4) [] = { 0x7d, 0x7d, 0x7d, 0x7d }; VECT_VAR_DECL(expected_rounding,uint,32,4) [] = { 0x7d, 0x7d, 0x7d, 0x7d }; /* Expected results for vcvt_n with rounding. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_vcvt_n_rounding, int, 16, 4) [] = +{ 0x533, 0x533, 0x533, 0x533 }; +VECT_VAR_DECL(expected_vcvt_n_rounding, uint, 16, 4) [] = +{ 0x533, 0x533, 0x533, 0x533 }; +VECT_VAR_DECL(expected_vcvt_n_rounding, int, 16, 8) [] = +{ 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff }; +VECT_VAR_DECL(expected_vcvt_n_rounding, uint, 16, 8) [] = +{ 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff }; +#endif VECT_VAR_DECL(expected_vcvt_n_rounding,int,32,2) [] = { 0xa66666, 0xa66666 }; VECT_VAR_DECL(expected_vcvt_n_rounding,uint,32,2) [] = { 0xa66666, 0xa66666 }; VECT_VAR_DECL(expected_vcvt_n_rounding,int,32,4) [] = { 0xfbccc, 0xfbccc, @@ -42,11 +105,17 @@ VECT_VAR_DECL(expected_vcvt_n_rounding,uint,32,4) [] = { 0xfbccc, 0xfbccc, 0xfbccc, 0xfbccc }; /* Expected results for vcvt_n with saturation. */ -VECT_VAR_DECL(expected_vcvt_n_saturation,int,32,2) [] = { 0x7fffffff, - 0x7fffffff }; -VECT_VAR_DECL(expected_vcvt_n_saturation,int,32,4) [] = { 0x7fffffff, - 0x7fffffff, - 0x7fffffff, 0x7fffffff }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_vcvt_n_saturation, int, 16, 4) [] = +{ 0x533, 0x533, 0x533, 0x533 }; +VECT_VAR_DECL(expected_vcvt_n_saturation, int, 16, 8) [] = +{ 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff }; +#endif +VECT_VAR_DECL(expected_vcvt_n_saturation,int,32,2) [] = +{ 0x7fffffff, 0x7fffffff }; +VECT_VAR_DECL(expected_vcvt_n_saturation,int,32,4) [] = +{ 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff }; #define TEST_MSG "VCVT/VCVTQ" void exec_vcvt (void) @@ -89,11 +158,26 @@ void exec_vcvt (void) /* Initialize input "vector" from "buffer". */ TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VLOAD(vector, buffer, , float, f, 16, 4); + VLOAD(vector, buffer, q, float, f, 16, 8); +#endif VLOAD(vector, buffer, , float, f, 32, 2); VLOAD(vector, buffer, q, float, f, 32, 4); /* Make sure some elements have a fractional part, to exercise integer conversions. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VSET_LANE(vector, , float, f, 16, 4, 0, -15.3f); + VSET_LANE(vector, , float, f, 16, 4, 1, 5.3f); + VSET_LANE(vector, , float, f, 16, 4, 2, -15.3f); + VSET_LANE(vector, , float, f, 16, 4, 3, 5.3f); + VSET_LANE(vector, q, float, f, 16, 8, 4, -15.3f); + VSET_LANE(vector, q, float, f, 16, 8, 5, 5.3f); + VSET_LANE(vector, q, float, f, 16, 8, 6, -15.3f); + VSET_LANE(vector, q, float, f, 16, 8, 7, 5.3f); +#endif + VSET_LANE(vector, , float, f, 32, 2, 0, -15.3f); VSET_LANE(vector, , float, f, 32, 2, 1, 5.3f); VSET_LANE(vector, q, float, f, 32, 4, 2, -15.3f); @@ -103,23 +187,55 @@ void exec_vcvt (void) before overwriting them. */ #define TEST_MSG2 "" +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + /* vcvt_f16_xx. */ + TEST_VCVT_FP(, float, f, 16, 4, int, s, expected_s); + TEST_VCVT_FP(, float, f, 16, 4, uint, u, expected_u); +#endif /* vcvt_f32_xx. */ TEST_VCVT_FP(, float, f, 32, 2, int, s, expected_s); TEST_VCVT_FP(, float, f, 32, 2, uint, u, expected_u); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + /* vcvtq_f16_xx. */ + TEST_VCVT_FP(q, float, f, 16, 8, int, s, expected_s); + TEST_VCVT_FP(q, float, f, 16, 8, uint, u, expected_u); +#endif /* vcvtq_f32_xx. */ TEST_VCVT_FP(q, float, f, 32, 4, int, s, expected_s); TEST_VCVT_FP(q, float, f, 32, 4, uint, u, expected_u); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + /* vcvt_xx_f16. */ + TEST_VCVT(, int, s, 16, 4, float, f, expected); + TEST_VCVT(, uint, u, 16, 4, float, f, expected); +#endif /* vcvt_xx_f32. */ TEST_VCVT(, int, s, 32, 2, float, f, expected); TEST_VCVT(, uint, u, 32, 2, float, f, expected); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VSET_LANE(vector, q, float, f, 16, 8, 0, 0.0f); + VSET_LANE(vector, q, float, f, 16, 8, 1, -0.0f); + VSET_LANE(vector, q, float, f, 16, 8, 2, 15.12f); + VSET_LANE(vector, q, float, f, 16, 8, 3, -15.12f); + VSET_LANE(vector, q, float, f, 16, 8, 4, 0.0f); + VSET_LANE(vector, q, float, f, 16, 8, 5, -0.0f); + VSET_LANE(vector, q, float, f, 16, 8, 6, 15.12f); + VSET_LANE(vector, q, float, f, 16, 8, 7, -15.12f); +#endif + VSET_LANE(vector, q, float, f, 32, 4, 0, 0.0f); VSET_LANE(vector, q, float, f, 32, 4, 1, -0.0f); VSET_LANE(vector, q, float, f, 32, 4, 2, 15.12f); VSET_LANE(vector, q, float, f, 32, 4, 3, -15.12f); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + /* vcvtq_xx_f16. */ + TEST_VCVT(q, int, s, 16, 8, float, f, expected); + TEST_VCVT(q, uint, u, 16, 8, float, f, expected); +#endif + /* vcvtq_xx_f32. */ TEST_VCVT(q, int, s, 32, 4, float, f, expected); TEST_VCVT(q, uint, u, 32, 4, float, f, expected); @@ -129,18 +245,38 @@ void exec_vcvt (void) #undef TEST_MSG #define TEST_MSG "VCVT_N/VCVTQ_N" +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + /* vcvt_n_f16_xx. */ + TEST_VCVT_N_FP(, float, f, 16, 4, int, s, 2, expected_vcvt_n_s); + TEST_VCVT_N_FP(, float, f, 16, 4, uint, u, 7, expected_vcvt_n_u); +#endif /* vcvt_n_f32_xx. */ TEST_VCVT_N_FP(, float, f, 32, 2, int, s, 2, expected_vcvt_n_s); TEST_VCVT_N_FP(, float, f, 32, 2, uint, u, 7, expected_vcvt_n_u); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + /* vcvtq_n_f16_xx. */ + TEST_VCVT_N_FP(q, float, f, 16, 8, int, s, 7, expected_vcvt_n_s); + TEST_VCVT_N_FP(q, float, f, 16, 8, uint, u, 12, expected_vcvt_n_u); +#endif /* vcvtq_n_f32_xx. */ TEST_VCVT_N_FP(q, float, f, 32, 4, int, s, 30, expected_vcvt_n_s); TEST_VCVT_N_FP(q, float, f, 32, 4, uint, u, 12, expected_vcvt_n_u); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + /* vcvt_n_xx_f16. */ + TEST_VCVT_N(, int, s, 16, 4, float, f, 2, expected_vcvt_n); + TEST_VCVT_N(, uint, u, 16, 4, float, f, 7, expected_vcvt_n); +#endif /* vcvt_n_xx_f32. */ TEST_VCVT_N(, int, s, 32, 2, float, f, 20, expected_vcvt_n); TEST_VCVT_N(, uint, u, 32, 2, float, f, 2, expected_vcvt_n); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + /* vcvtq_n_xx_f16. */ + TEST_VCVT_N(q, int, s, 16, 8, float, f, 7, expected_vcvt_n); + TEST_VCVT_N(q, uint, u, 16, 8, float, f, 12, expected_vcvt_n); +#endif /* vcvtq_n_xx_f32. */ TEST_VCVT_N(q, int, s, 32, 4, float, f, 13, expected_vcvt_n); TEST_VCVT_N(q, uint, u, 32, 4, float, f, 1, expected_vcvt_n); @@ -150,20 +286,49 @@ void exec_vcvt (void) #define TEST_MSG "VCVT/VCVTQ" #undef TEST_MSG2 #define TEST_MSG2 "(check rounding)" + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector, , float, f, 16, 4, 10.4f); + VDUP(vector, q, float, f, 16, 8, 125.9f); +#endif VDUP(vector, , float, f, 32, 2, 10.4f); VDUP(vector, q, float, f, 32, 4, 125.9f); + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + /* vcvt_xx_f16. */ + TEST_VCVT(, int, s, 16, 4, float, f, expected_rounding); + TEST_VCVT(, uint, u, 16, 4, float, f, expected_rounding); +#endif /* vcvt_xx_f32. */ TEST_VCVT(, int, s, 32, 2, float, f, expected_rounding); TEST_VCVT(, uint, u, 32, 2, float, f, expected_rounding); + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + /* vcvtq_xx_f16. */ + TEST_VCVT(q, int, s, 16, 8, float, f, expected_rounding); + TEST_VCVT(q, uint, u, 16, 8, float, f, expected_rounding); +#endif /* vcvtq_xx_f32. */ TEST_VCVT(q, int, s, 32, 4, float, f, expected_rounding); TEST_VCVT(q, uint, u, 32, 4, float, f, expected_rounding); #undef TEST_MSG #define TEST_MSG "VCVT_N/VCVTQ_N" + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + /* vcvt_n_xx_f16. */ + TEST_VCVT_N(, int, s, 16, 4, float, f, 7, expected_vcvt_n_rounding); + TEST_VCVT_N(, uint, u, 16, 4, float, f, 7, expected_vcvt_n_rounding); +#endif /* vcvt_n_xx_f32. */ TEST_VCVT_N(, int, s, 32, 2, float, f, 20, expected_vcvt_n_rounding); TEST_VCVT_N(, uint, u, 32, 2, float, f, 20, expected_vcvt_n_rounding); + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + /* vcvtq_n_xx_f16. */ + TEST_VCVT_N(q, int, s, 16, 8, float, f, 13, expected_vcvt_n_rounding); + TEST_VCVT_N(q, uint, u, 16, 8, float, f, 13, expected_vcvt_n_rounding); +#endif /* vcvtq_n_xx_f32. */ TEST_VCVT_N(q, int, s, 32, 4, float, f, 13, expected_vcvt_n_rounding); TEST_VCVT_N(q, uint, u, 32, 4, float, f, 13, expected_vcvt_n_rounding); @@ -172,8 +337,18 @@ void exec_vcvt (void) #define TEST_MSG "VCVT_N/VCVTQ_N" #undef TEST_MSG2 #define TEST_MSG2 "(check saturation)" + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + /* vcvt_n_xx_f16. */ + TEST_VCVT_N(, int, s, 16, 4, float, f, 7, expected_vcvt_n_saturation); +#endif /* vcvt_n_xx_f32. */ TEST_VCVT_N(, int, s, 32, 2, float, f, 31, expected_vcvt_n_saturation); + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + /* vcvtq_n_xx_f16. */ + TEST_VCVT_N(q, int, s, 16, 8, float, f, 13, expected_vcvt_n_saturation); +#endif /* vcvtq_n_xx_f32. */ TEST_VCVT_N(q, int, s, 32, 4, float, f, 31, expected_vcvt_n_saturation); } diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtX.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtX.inc new file mode 100644 index 00000000000..e0a479f5bbe --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtX.inc @@ -0,0 +1,113 @@ +/* Template file for VCVT operator validation. + + This file is meant to be included by the relevant test files, which + have to define the intrinsic family to test. If a given intrinsic + supports variants which are not supported by all the other vcvt + operators, these can be tested by providing a definition for + EXTRA_TESTS. + + This file is only used for VCVT? tests, which currently have only f16 to + integer variants. It is based on vcvt.c. */ + +#define FNNAME1(NAME) exec_ ## NAME +#define FNNAME(NAME) FNNAME1 (NAME) + +void FNNAME (INSN_NAME) (void) +{ + int i; + + /* Basic test: y=vcvt(x), then store the result. */ +#define TEST_VCVT1(INSN, Q, T1, T2, W, N, TS1, TS2, EXP) \ + VECT_VAR(vector_res, T1, W, N) = \ + INSN##Q##_##T2##W##_##TS2##W(VECT_VAR(vector, TS1, W, N)); \ + vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \ + VECT_VAR(vector_res, T1, W, N)); \ + CHECK(TEST_MSG, T1, W, N, PRIx##W, EXP, TEST_MSG2); + +#define TEST_VCVT(INSN, Q, T1, T2, W, N, TS1, TS2, EXP) \ + TEST_VCVT1 (INSN, Q, T1, T2, W, N, TS1, TS2, EXP) + + DECL_VARIABLE_ALL_VARIANTS(vector); + DECL_VARIABLE_ALL_VARIANTS(vector_res); + + clean_results (); + + /* Initialize input "vector" from "buffer". */ + TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VLOAD(vector, buffer, , float, f, 16, 4); + VLOAD(vector, buffer, q, float, f, 16, 8); +#endif + + /* Make sure some elements have a fractional part, to exercise + integer conversions. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VSET_LANE(vector, , float, f, 16, 4, 0, -15.3f); + VSET_LANE(vector, , float, f, 16, 4, 1, 5.3f); + VSET_LANE(vector, , float, f, 16, 4, 2, -15.3f); + VSET_LANE(vector, , float, f, 16, 4, 3, 5.3f); + VSET_LANE(vector, q, float, f, 16, 8, 4, -15.3f); + VSET_LANE(vector, q, float, f, 16, 8, 5, 5.3f); + VSET_LANE(vector, q, float, f, 16, 8, 6, -15.3f); + VSET_LANE(vector, q, float, f, 16, 8, 7, 5.3f); +#endif + + /* The same result buffers are used multiple times, so we check them + before overwriting them. */ +#define TEST_MSG2 "" + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + /* vcvt?_xx_f16. */ + TEST_VCVT(INSN_NAME, , int, s, 16, 4, float, f, expected); + TEST_VCVT(INSN_NAME, , uint, u, 16, 4, float, f, expected); +#endif + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VSET_LANE(vector, q, float, f, 16, 8, 0, 0.0f); + VSET_LANE(vector, q, float, f, 16, 8, 1, -0.0f); + VSET_LANE(vector, q, float, f, 16, 8, 2, 15.12f); + VSET_LANE(vector, q, float, f, 16, 8, 3, -15.12f); + VSET_LANE(vector, q, float, f, 16, 8, 4, 0.0f); + VSET_LANE(vector, q, float, f, 16, 8, 5, -0.0f); + VSET_LANE(vector, q, float, f, 16, 8, 6, 15.12f); + VSET_LANE(vector, q, float, f, 16, 8, 7, -15.12f); +#endif + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + /* vcvt?q_xx_f16. */ + TEST_VCVT(INSN_NAME, q, int, s, 16, 8, float, f, expected); + TEST_VCVT(INSN_NAME, q, uint, u, 16, 8, float, f, expected); +#endif + + /* Check rounding. */ +#undef TEST_MSG2 +#define TEST_MSG2 "(check rounding)" + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector, , float, f, 16, 4, 10.4f); + VDUP(vector, q, float, f, 16, 8, 125.9f); +#endif + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + /* vcvt?_xx_f16. */ + TEST_VCVT(INSN_NAME, , int, s, 16, 4, float, f, expected_rounding); + TEST_VCVT(INSN_NAME, , uint, u, 16, 4, float, f, expected_rounding); +#endif + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + /* vcvt?q_xx_f16. */ + TEST_VCVT(INSN_NAME, q, int, s, 16, 8, float, f, expected_rounding); + TEST_VCVT(INSN_NAME, q, uint, u, 16, 8, float, f, expected_rounding); +#endif + +#ifdef EXTRA_TESTS + EXTRA_TESTS(); +#endif +} + +int +main (void) +{ + FNNAME (INSN_NAME) (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvta_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvta_1.c new file mode 100644 index 00000000000..c467f053145 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvta_1.c @@ -0,0 +1,33 @@ +/* This file tests an intrinsic which currently has only an f16 variant and that + is only available when FP16 arithmetic instructions are supported. */ +/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ + +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" +#include + +/* Expected results. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected, int, 16, 4) [] = { 0xfff1, 0x5, 0xfff1, 0x5 }; +VECT_VAR_DECL(expected, uint, 16, 4) [] = { 0x0, 0x5, 0x0, 0x5 }; +VECT_VAR_DECL(expected, int, 16, 8) [] = { 0x0, 0x0, 0xf, 0xfff1, + 0x0, 0x0, 0xf, 0xfff1 }; +VECT_VAR_DECL(expected, uint, 16, 8) [] = { 0x0, 0x0, 0xf, 0x0, + 0x0, 0x0, 0xf, 0x0 }; +#endif + +/* Expected results with rounding. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_rounding, int, 16, 4) [] = { 0xa, 0xa, 0xa, 0xa }; +VECT_VAR_DECL(expected_rounding, uint, 16, 4) [] = { 0xa, 0xa, 0xa, 0xa }; +VECT_VAR_DECL(expected_rounding, int, 16, 8) [] = { 0x7e, 0x7e, 0x7e, 0x7e, + 0x7e, 0x7e, 0x7e, 0x7e }; +VECT_VAR_DECL(expected_rounding, uint, 16, 8) [] = { 0x7e, 0x7e, 0x7e, 0x7e, + 0x7e, 0x7e, 0x7e, 0x7e }; +#endif + +#define TEST_MSG "VCVTA/VCVTAQ" +#define INSN_NAME vcvta + +#include "vcvtX.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtm_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtm_1.c new file mode 100644 index 00000000000..1c227729bf8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtm_1.c @@ -0,0 +1,33 @@ +/* This file tests an intrinsic which currently has only an f16 variant and that + is only available when FP16 arithmetic instructions are supported. */ +/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ + +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" +#include + +/* Expected results. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected, int, 16, 4) [] = { 0xfff0, 0x5, 0xfff0, 0x5 }; +VECT_VAR_DECL(expected, uint, 16, 4) [] = { 0x0, 0x5, 0x0, 0x5 }; +VECT_VAR_DECL(expected, int, 16, 8) [] = { 0x0, 0x0, 0xf, 0xfff0, 0x0, + 0x0, 0xf, 0xfff0 }; +VECT_VAR_DECL(expected, uint, 16, 8) [] = { 0x0, 0x0, 0xf, 0x0, + 0x0, 0x0, 0xf, 0x0 }; +#endif + +/* Expected results with rounding. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_rounding, int, 16, 4) [] = { 0xa, 0xa, 0xa, 0xa }; +VECT_VAR_DECL(expected_rounding, uint, 16, 4) [] = { 0xa, 0xa, 0xa, 0xa }; +VECT_VAR_DECL(expected_rounding, int, 16, 8) [] = { 0x7d, 0x7d, 0x7d, 0x7d, + 0x7d, 0x7d, 0x7d, 0x7d }; +VECT_VAR_DECL(expected_rounding, uint, 16, 8) [] = { 0x7d, 0x7d, 0x7d, 0x7d, + 0x7d, 0x7d, 0x7d, 0x7d }; +#endif + +#define TEST_MSG "VCVTM/VCVTMQ" +#define INSN_NAME vcvtm + +#include "vcvtX.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtp_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtp_1.c new file mode 100644 index 00000000000..7057909f855 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtp_1.c @@ -0,0 +1,33 @@ +/* This file tests an intrinsic which currently has only an f16 variant and that + is only available when FP16 arithmetic instructions are supported. */ +/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ + +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" +#include + +/* Expected results. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected, int, 16, 4) [] = { 0xfff1, 0x6, 0xfff1, 0x6 }; +VECT_VAR_DECL(expected, uint, 16, 4) [] = { 0x0, 0x6, 0x0, 0x6 }; +VECT_VAR_DECL(expected, int, 16, 8) [] = { 0x0, 0x0, 0x10, 0xfff1, + 0x0, 0x0, 0x10, 0xfff1 }; +VECT_VAR_DECL(expected, uint, 16, 8) [] = { 0x0, 0x0, 0x10, 0x0, + 0x0, 0x0, 0x10, 0x0 }; +#endif + +/* Expected results with rounding. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_rounding, int, 16, 4) [] = { 0xb, 0xb, 0xb, 0xb }; +VECT_VAR_DECL(expected_rounding, uint, 16, 4) [] = { 0xb, 0xb, 0xb, 0xb }; +VECT_VAR_DECL(expected_rounding, int, 16, 8) [] = { 0x7e, 0x7e, 0x7e, 0x7e, + 0x7e, 0x7e, 0x7e, 0x7e }; +VECT_VAR_DECL(expected_rounding, uint, 16, 8) [] = { 0x7e, 0x7e, 0x7e, 0x7e, + 0x7e, 0x7e, 0x7e, 0x7e }; +#endif + +#define TEST_MSG "VCVTP/VCVTPQ" +#define INSN_NAME vcvtp + +#include "vcvtX.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfma.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfma.c index 8180108d528..2cf68fe895d 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfma.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfma.c @@ -3,11 +3,19 @@ #include "compute-ref-data.h" #ifdef __ARM_FEATURE_FMA + /* Expected results. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0x61c6, 0x61c8, 0x61ca, 0x61cc }; +VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0x6435, 0x6436, 0x6437, 0x6438, + 0x6439, 0x643a, 0x643b, 0x643c }; +#endif VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x4438ca3d, 0x44390a3d }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x44869eb8, 0x4486beb8, 0x4486deb8, 0x4486feb8 }; +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x44869eb8, 0x4486beb8, + 0x4486deb8, 0x4486feb8 }; #ifdef __aarch64__ -VECT_VAR_DECL(expected,hfloat,64,2) [] = { 0x408906e1532b8520, 0x40890ee1532b8520 }; +VECT_VAR_DECL(expected,hfloat,64,2) [] = { 0x408906e1532b8520, + 0x40890ee1532b8520 }; #endif #define TEST_MSG "VFMA/VFMAQ" @@ -44,6 +52,18 @@ void exec_vfma (void) DECL_VARIABLE(VAR, float, 32, 4); #endif +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector1, float, 16, 4); + DECL_VARIABLE(vector2, float, 16, 4); + DECL_VARIABLE(vector3, float, 16, 4); + DECL_VARIABLE(vector_res, float, 16, 4); + + DECL_VARIABLE(vector1, float, 16, 8); + DECL_VARIABLE(vector2, float, 16, 8); + DECL_VARIABLE(vector3, float, 16, 8); + DECL_VARIABLE(vector_res, float, 16, 8); +#endif + DECL_VFMA_VAR(vector1); DECL_VFMA_VAR(vector2); DECL_VFMA_VAR(vector3); @@ -52,6 +72,10 @@ void exec_vfma (void) clean_results (); /* Initialize input "vector1" from "buffer". */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VLOAD(vector1, buffer, , float, f, 16, 4); + VLOAD(vector1, buffer, q, float, f, 16, 8); +#endif VLOAD(vector1, buffer, , float, f, 32, 2); VLOAD(vector1, buffer, q, float, f, 32, 4); #ifdef __aarch64__ @@ -59,13 +83,21 @@ void exec_vfma (void) #endif /* Choose init value arbitrarily. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector2, , float, f, 16, 4, 9.3f); + VDUP(vector2, q, float, f, 16, 8, 29.7f); +#endif VDUP(vector2, , float, f, 32, 2, 9.3f); VDUP(vector2, q, float, f, 32, 4, 29.7f); #ifdef __aarch64__ VDUP(vector2, q, float, f, 64, 2, 15.8f); #endif - + /* Choose init value arbitrarily. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector3, , float, f, 16, 4, 81.2f); + VDUP(vector3, q, float, f, 16, 8, 36.8f); +#endif VDUP(vector3, , float, f, 32, 2, 81.2f); VDUP(vector3, q, float, f, 32, 4, 36.8f); #ifdef __aarch64__ @@ -73,12 +105,20 @@ void exec_vfma (void) #endif /* Execute the tests. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VFMA(, float, f, 16, 4); + TEST_VFMA(q, float, f, 16, 8); +#endif TEST_VFMA(, float, f, 32, 2); TEST_VFMA(q, float, f, 32, 4); #ifdef __aarch64__ TEST_VFMA(q, float, f, 64, 2); #endif +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, ""); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, ""); +#endif CHECK_VFMA_RESULTS (TEST_MSG, ""); } #endif diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfms.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfms.c index 02bef09d487..555654d0ac5 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfms.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfms.c @@ -4,10 +4,17 @@ #ifdef __ARM_FEATURE_FMA /* Expected results. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xe206, 0xe204, 0xe202, 0xe200 }; +VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xe455, 0xe454, 0xe453, 0xe452, + 0xe451, 0xe450, 0xe44f, 0xe44e }; +#endif VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc440ca3d, 0xc4408a3d }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc48a9eb8, 0xc48a7eb8, 0xc48a5eb8, 0xc48a3eb8 }; +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc48a9eb8, 0xc48a7eb8, + 0xc48a5eb8, 0xc48a3eb8 }; #ifdef __aarch64__ -VECT_VAR_DECL(expected,hfloat,64,2) [] = { 0xc08a06e1532b8520, 0xc089fee1532b8520 }; +VECT_VAR_DECL(expected,hfloat,64,2) [] = { 0xc08a06e1532b8520, + 0xc089fee1532b8520 }; #endif #define TEST_MSG "VFMS/VFMSQ" @@ -44,6 +51,18 @@ void exec_vfms (void) DECL_VARIABLE(VAR, float, 32, 4); #endif +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector1, float, 16, 4); + DECL_VARIABLE(vector2, float, 16, 4); + DECL_VARIABLE(vector3, float, 16, 4); + DECL_VARIABLE(vector_res, float, 16, 4); + + DECL_VARIABLE(vector1, float, 16, 8); + DECL_VARIABLE(vector2, float, 16, 8); + DECL_VARIABLE(vector3, float, 16, 8); + DECL_VARIABLE(vector_res, float, 16, 8); +#endif + DECL_VFMS_VAR(vector1); DECL_VFMS_VAR(vector2); DECL_VFMS_VAR(vector3); @@ -52,6 +71,10 @@ void exec_vfms (void) clean_results (); /* Initialize input "vector1" from "buffer". */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VLOAD(vector1, buffer, , float, f, 16, 4); + VLOAD(vector1, buffer, q, float, f, 16, 8); +#endif VLOAD(vector1, buffer, , float, f, 32, 2); VLOAD(vector1, buffer, q, float, f, 32, 4); #ifdef __aarch64__ @@ -59,13 +82,21 @@ void exec_vfms (void) #endif /* Choose init value arbitrarily. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector2, , float, f, 16, 4, 9.3f); + VDUP(vector2, q, float, f, 16, 8, 29.7f); +#endif VDUP(vector2, , float, f, 32, 2, 9.3f); VDUP(vector2, q, float, f, 32, 4, 29.7f); #ifdef __aarch64__ VDUP(vector2, q, float, f, 64, 2, 15.8f); #endif - + /* Choose init value arbitrarily. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector3, , float, f, 16, 4, 81.2f); + VDUP(vector3, q, float, f, 16, 8, 36.8f); +#endif VDUP(vector3, , float, f, 32, 2, 81.2f); VDUP(vector3, q, float, f, 32, 4, 36.8f); #ifdef __aarch64__ @@ -73,12 +104,20 @@ void exec_vfms (void) #endif /* Execute the tests. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VFMS(, float, f, 16, 4); + TEST_VFMS(q, float, f, 16, 8); +#endif TEST_VFMS(, float, f, 32, 2); TEST_VFMS(q, float, f, 32, 4); #ifdef __aarch64__ TEST_VFMS(q, float, f, 64, 2); #endif +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, ""); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, ""); +#endif CHECK_VFMS_RESULTS (TEST_MSG, ""); } #endif diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c index 830603dff6a..80f8bec1212 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c @@ -7,6 +7,10 @@ #define HAS_FLOAT_VARIANT +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +#define HAS_FLOAT16_VARIANT +#endif + /* Expected results. */ VECT_VAR_DECL(expected,int,8,8) [] = { 0xf3, 0xf3, 0xf3, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }; @@ -16,6 +20,9 @@ VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf3, 0xf3, 0xf3, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }; VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff1, 0xfff2, 0xfff3 }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xcbc0, 0xcb80, 0xcb00, 0xca80 }; +#endif VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1780000, 0xc1700000 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0xf4, 0xf4, 0xf4, 0xf4, 0xf4, 0xf5, 0xf6, 0xf7, @@ -33,10 +40,36 @@ VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff2, 0xfff2, 0xfff2, 0xfff3, 0xfff4, 0xfff5, 0xfff6, 0xfff7 }; VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff1, 0xfffffff1, 0xfffffff2, 0xfffffff3 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xcb40, 0xcb40, 0xcb00, 0xca80, + 0xca00, 0xc980, 0xc900, 0xc880 }; +#endif VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1680000, 0xc1680000, 0xc1600000, 0xc1500000 }; /* Expected results with special FP values. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_nan, hfloat, 16, 8) [] = { 0x7e00, 0x7e00, + 0x7e00, 0x7e00, + 0x7e00, 0x7e00, + 0x7e00, 0x7e00 }; +VECT_VAR_DECL(expected_mnan, hfloat, 16, 8) [] = { 0x7e00, 0x7e00, + 0x7e00, 0x7e00, + 0x7e00, 0x7e00, + 0x7e00, 0x7e00 }; +VECT_VAR_DECL(expected_inf, hfloat, 16, 8) [] = { 0x7c00, 0x7c00, + 0x7c00, 0x7c00, + 0x7c00, 0x7c00, + 0x7c00, 0x7c00 }; +VECT_VAR_DECL(expected_minf, hfloat, 16, 8) [] = { 0x3c00, 0x3c00, + 0x3c00, 0x3c00, + 0x3c00, 0x3c00, + 0x3c00, 0x3c00 }; +VECT_VAR_DECL(expected_zero1, hfloat, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL(expected_zero2, hfloat, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0 }; +#endif VECT_VAR_DECL(expected_nan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000 }; VECT_VAR_DECL(expected_mnan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000, diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnm_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnm_1.c new file mode 100644 index 00000000000..e546bd5367e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnm_1.c @@ -0,0 +1,47 @@ +/* This file tests an intrinsic which currently has only an f16 variant and that + is only available when FP16 arithmetic instructions are supported. */ +/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ + +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#define INSN_NAME vmaxnm +#define TEST_MSG "VMAXNM/VMAXNMQ" + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +#define HAS_FLOAT16_VARIANT +#endif + +/* Expected results. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xcbc0, 0xcb80, 0xcb00, 0xca80 }; +VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xcb40, 0xcb40, 0xcb00, 0xca80, + 0xca00, 0xc980, 0xc900, 0xc880 }; +#endif + +/* Expected results with special FP values. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_nan, hfloat, 16, 8) [] = { 0x3c00, 0x3c00, + 0x3c00, 0x3c00, + 0x3c00, 0x3c00, + 0x3c00, 0x3c00 }; +VECT_VAR_DECL(expected_mnan, hfloat, 16, 8) [] = { 0x3c00, 0x3c00, + 0x3c00, 0x3c00, + 0x3c00, 0x3c00, + 0x3c00, 0x3c00 }; +VECT_VAR_DECL(expected_inf, hfloat, 16, 8) [] = { 0x7c00, 0x7c00, + 0x7c00, 0x7c00, + 0x7c00, 0x7c00, + 0x7c00, 0x7c00 }; +VECT_VAR_DECL(expected_minf, hfloat, 16, 8) [] = { 0x3c00, 0x3c00, + 0x3c00, 0x3c00, + 0x3c00, 0x3c00, + 0x3c00, 0x3c00 }; +VECT_VAR_DECL(expected_zero1, hfloat, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL(expected_zero2, hfloat, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0 }; +#endif + +#include "binary_op_float.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c index 8ad2703c3db..4ee3c1ee77f 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c @@ -7,6 +7,10 @@ #define HAS_FLOAT_VARIANT +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +#define HAS_FLOAT16_VARIANT +#endif + /* Expected results. */ VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf3, 0xf3, 0xf3, 0xf3 }; @@ -16,6 +20,9 @@ VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf3, 0xf3, 0xf3, 0xf3 }; VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff1, 0xfff1 }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xcc00, 0xcbc0, 0xcbc0, 0xcbc0 }; +#endif VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1780000 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf4, 0xf4, 0xf4, @@ -31,11 +38,41 @@ VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf9, 0xf9, 0xf9, 0xf9 }; VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff2, 0xfff2, 0xfff2, 0xfff2, 0xfff2 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb80, 0xcb40, 0xcb40, + 0xcb40, 0xcb40, 0xcb40, 0xcb40 }; +#endif VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff0, 0xfffffff1, 0xfffffff1, 0xfffffff1 }; VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800000, 0xc1700000, 0xc1680000, 0xc1680000 }; /* Expected results with special FP values. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_nan, hfloat, 16, 8) [] = { 0x7e00, 0x7e00, + 0x7e00, 0x7e00, + 0x7e00, 0x7e00, + 0x7e00, 0x7e00 }; +VECT_VAR_DECL(expected_mnan, hfloat, 16, 8) [] = { 0x7e00, 0x7e00, + 0x7e00, 0x7e00, + 0x7e00, 0x7e00, + 0x7e00, 0x7e00 }; +VECT_VAR_DECL(expected_inf, hfloat, 16, 8) [] = { 0x3c00, 0x3c00, + 0x3c00, 0x3c00, + 0x3c00, 0x3c00, + 0x3c00, 0x3c00 }; +VECT_VAR_DECL(expected_minf, hfloat, 16, 8) [] = { 0xfc00, 0xfc00, + 0xfc00, 0xfc00, + 0xfc00, 0xfc00, + 0xfc00, 0xfc00 }; +VECT_VAR_DECL(expected_zero1, hfloat, 16, 8) [] = { 0x8000, 0x8000, + 0x8000, 0x8000, + 0x8000, 0x8000, + 0x8000, 0x8000 }; +VECT_VAR_DECL(expected_zero2, hfloat, 16, 8) [] = { 0x8000, 0x8000, + 0x8000, 0x8000, + 0x8000, 0x8000, + 0x8000, 0x8000 }; +#endif VECT_VAR_DECL(expected_nan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000 }; VECT_VAR_DECL(expected_mnan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000, diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnm_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnm_1.c new file mode 100644 index 00000000000..975fc56bbb1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnm_1.c @@ -0,0 +1,51 @@ +/* This file tests an intrinsic which currently has only an f16 variant and that + is only available when FP16 arithmetic instructions are supported. */ +/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ + +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#define INSN_NAME vminnm +#define TEST_MSG "VMINNM/VMINMQ" + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +#define HAS_FLOAT16_VARIANT +#endif + +/* Expected results. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xcc00, 0xcbc0, 0xcbc0, 0xcbc0 }; +VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb80, 0xcb40, 0xcb40, + 0xcb40, 0xcb40, 0xcb40, 0xcb40 }; +#endif + +/* Expected results with special FP values. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_nan, hfloat, 16, 8) [] = { 0x3c00, 0x3c00, + 0x3c00, 0x3c00, + 0x3c00, 0x3c00, + 0x3c00, 0x3c00 }; +VECT_VAR_DECL(expected_mnan, hfloat, 16, 8) [] = { 0x3c00, 0x3c00, + 0x3c00, 0x3c00, + 0x3c00, 0x3c00, + 0x3c00, 0x3c00 }; +VECT_VAR_DECL(expected_inf, hfloat, 16, 8) [] = { 0x3c00, 0x3c00, + 0x3c00, 0x3c00, + 0x3c00, 0x3c00, + 0x3c00, 0x3c00 }; +VECT_VAR_DECL(expected_minf, hfloat, 16, 8) [] = { 0xfc00, 0xfc00, + 0xfc00, 0xfc00, + 0xfc00, 0xfc00, + 0xfc00, 0xfc00 }; +VECT_VAR_DECL(expected_zero1, hfloat, 16, 8) [] = { 0x8000, 0x8000, + 0x8000, 0x8000, + 0x8000, 0x8000, + 0x8000, 0x8000 }; +VECT_VAR_DECL(expected_zero2, hfloat, 16, 8) [] = { 0x8000, 0x8000, + 0x8000, 0x8000, + 0x8000, 0x8000, + 0x8000, 0x8000 }; +#endif + +#include "binary_op_float.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul.c index 63f0d8d6320..c5fe31a56fb 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul.c @@ -13,6 +13,10 @@ VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfab0, 0xfb05, 0xfb5a, 0xfbaf }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffff9a0, 0xfffffa06 }; VECT_VAR_DECL(expected,poly,8,8) [] = { 0xc0, 0x84, 0x48, 0xc, 0xd0, 0x94, 0x58, 0x1c }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xe02a, 0xdfcf, + 0xdf4a, 0xdec4 }; +#endif VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc4053333, 0xc3f9c000 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0x90, 0x7, 0x7e, 0xf5, 0x6c, 0xe3, 0x5a, 0xd1, @@ -34,6 +38,10 @@ VECT_VAR_DECL(expected,poly,8,16) [] = { 0x60, 0xca, 0x34, 0x9e, 0xc8, 0x62, 0x9c, 0x36, 0x30, 0x9a, 0x64, 0xce, 0x98, 0x32, 0xcc, 0x66 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xe63a, 0xe5d6, 0xe573, 0xe50f, + 0xe4ac, 0xe448, 0xe3c8, 0xe301 }; +#endif VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc4c73333, 0xc4bac000, 0xc4ae4ccd, 0xc4a1d999 }; @@ -78,6 +86,17 @@ void FNNAME (INSN_NAME) (void) DECL_VMUL(poly, 8, 16); DECL_VMUL(float, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector1, float, 16, 4); + DECL_VARIABLE(vector1, float, 16, 8); + + DECL_VARIABLE(vector2, float, 16, 4); + DECL_VARIABLE(vector2, float, 16, 8); + + DECL_VARIABLE(vector_res, float, 16, 4); + DECL_VARIABLE(vector_res, float, 16, 8); +#endif + clean_results (); /* Initialize input "vector1" from "buffer". */ @@ -97,6 +116,10 @@ void FNNAME (INSN_NAME) (void) VLOAD(vector1, buffer, q, uint, u, 32, 4); VLOAD(vector1, buffer, q, poly, p, 8, 16); VLOAD(vector1, buffer, q, float, f, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VLOAD(vector1, buffer, , float, f, 16, 4); + VLOAD(vector1, buffer, q, float, f, 16, 8); +#endif /* Choose init value arbitrarily. */ VDUP(vector2, , int, s, 8, 8, 0x11); @@ -115,6 +138,10 @@ void FNNAME (INSN_NAME) (void) VDUP(vector2, q, uint, u, 32, 4, 0xCC); VDUP(vector2, q, poly, p, 8, 16, 0xAA); VDUP(vector2, q, float, f, 32, 4, 99.6f); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector2, , float, f, 16, 4, 33.3f); + VDUP(vector2, q, float, f, 16, 8, 99.6f); +#endif /* Execute the tests. */ TEST_VMUL(INSN_NAME, , int, s, 8, 8); @@ -133,6 +160,10 @@ void FNNAME (INSN_NAME) (void) TEST_VMUL(INSN_NAME, q, uint, u, 32, 4); TEST_VMUL(INSN_NAME, q, poly, p, 8, 16); TEST_VMUL(INSN_NAME, q, float, f, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VMUL(INSN_NAME, , float, f, 16, 4); + TEST_VMUL(INSN_NAME, q, float, f, 16, 8); +#endif CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, ""); CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, ""); @@ -150,6 +181,10 @@ void FNNAME (INSN_NAME) (void) CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, ""); CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected, ""); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, ""); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, ""); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, ""); +#endif } int main (void) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c index 978cd9b477d..e6cf4d72c37 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c @@ -7,6 +7,9 @@ VECT_VAR_DECL(expected,int,16,4) [] = { 0xffc0, 0xffc4, 0xffc8, 0xffcc }; VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffde0, 0xfffffe02 }; VECT_VAR_DECL(expected,uint,16,4) [] = { 0xbbc0, 0xc004, 0xc448, 0xc88c }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffface0, 0xffffb212 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xddb3, 0xdd58, 0xdcfd, 0xdca1 }; +#endif VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc3b66666, 0xc3ab0000 }; VECT_VAR_DECL(expected,int,16,8) [] = { 0xffc0, 0xffc4, 0xffc8, 0xffcc, 0xffd0, 0xffd4, 0xffd8, 0xffdc }; @@ -16,6 +19,10 @@ VECT_VAR_DECL(expected,uint,16,8) [] = { 0xbbc0, 0xc004, 0xc448, 0xc88c, 0xccd0, 0xd114, 0xd558, 0xd99c }; VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffface0, 0xffffb212, 0xffffb744, 0xffffbc76 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xddb3, 0xdd58, 0xdcfd, 0xdca1, + 0xdc46, 0xdbd6, 0xdb20, 0xda69 }; +#endif VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc3b66666, 0xc3ab0000, 0xc39f9999, 0xc3943333 }; @@ -45,11 +52,20 @@ void exec_vmul_lane (void) DECL_VMUL(vector); DECL_VMUL(vector_res); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector, float, 16, 4); + DECL_VARIABLE(vector, float, 16, 8); + DECL_VARIABLE(vector_res, float, 16, 4); + DECL_VARIABLE(vector_res, float, 16, 8); +#endif DECL_VARIABLE(vector2, int, 16, 4); DECL_VARIABLE(vector2, int, 32, 2); DECL_VARIABLE(vector2, uint, 16, 4); DECL_VARIABLE(vector2, uint, 32, 2); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector2, float, 16, 4); +#endif DECL_VARIABLE(vector2, float, 32, 2); clean_results (); @@ -59,11 +75,17 @@ void exec_vmul_lane (void) VLOAD(vector, buffer, , int, s, 32, 2); VLOAD(vector, buffer, , uint, u, 16, 4); VLOAD(vector, buffer, , uint, u, 32, 2); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VLOAD(vector, buffer, , float, f, 16, 4); +#endif VLOAD(vector, buffer, , float, f, 32, 2); VLOAD(vector, buffer, q, int, s, 16, 8); VLOAD(vector, buffer, q, int, s, 32, 4); VLOAD(vector, buffer, q, uint, u, 16, 8); VLOAD(vector, buffer, q, uint, u, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VLOAD(vector, buffer, q, float, f, 16, 8); +#endif VLOAD(vector, buffer, q, float, f, 32, 4); /* Initialize vector2. */ @@ -71,6 +93,9 @@ void exec_vmul_lane (void) VDUP(vector2, , int, s, 32, 2, 0x22); VDUP(vector2, , uint, u, 16, 4, 0x444); VDUP(vector2, , uint, u, 32, 2, 0x532); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector2, , float, f, 16, 4, 22.8f); +#endif VDUP(vector2, , float, f, 32, 2, 22.8f); /* Choose lane arbitrarily. */ @@ -78,22 +103,34 @@ void exec_vmul_lane (void) TEST_VMUL_LANE(, int, s, 32, 2, 2, 1); TEST_VMUL_LANE(, uint, u, 16, 4, 4, 2); TEST_VMUL_LANE(, uint, u, 32, 2, 2, 1); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VMUL_LANE(, float, f, 16, 4, 4, 1); +#endif TEST_VMUL_LANE(, float, f, 32, 2, 2, 1); TEST_VMUL_LANE(q, int, s, 16, 8, 4, 2); TEST_VMUL_LANE(q, int, s, 32, 4, 2, 0); TEST_VMUL_LANE(q, uint, u, 16, 8, 4, 2); TEST_VMUL_LANE(q, uint, u, 32, 4, 2, 1); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VMUL_LANE(q, float, f, 16, 8, 4, 0); +#endif TEST_VMUL_LANE(q, float, f, 32, 4, 2, 0); CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, ""); CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, ""); CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, ""); CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, ""); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, ""); +#endif CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, ""); CHECK(TEST_MSG, int, 16, 8, PRIx64, expected, ""); CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, ""); CHECK(TEST_MSG, uint, 16, 8, PRIx64, expected, ""); CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, ""); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, ""); +#endif CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, ""); } diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_n.c index be0ee65cc65..16f7dac6b0b 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_n.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_n.c @@ -7,6 +7,9 @@ VECT_VAR_DECL(expected,int,16,4) [] = { 0xfef0, 0xff01, 0xff12, 0xff23 }; VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffde0, 0xfffffe02 }; VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfcd0, 0xfd03, 0xfd36, 0xfd69 }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffbc0, 0xfffffc04 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xdd93, 0xdd3a, 0xdce1, 0xdc87 }; +#endif VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc3b26666, 0xc3a74000 }; VECT_VAR_DECL(expected,int,16,8) [] = { 0xfab0, 0xfb05, 0xfb5a, 0xfbaf, 0xfc04, 0xfc59, 0xfcae, 0xfd03 }; @@ -16,6 +19,10 @@ VECT_VAR_DECL(expected,uint,16,8) [] = { 0xf890, 0xf907, 0xf97e, 0xf9f5, 0xfa6c, 0xfae3, 0xfb5a, 0xfbd1 }; VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffff780, 0xfffff808, 0xfffff890, 0xfffff918 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xe58e, 0xe535, 0xe4dc, 0xe483, + 0xe42a, 0xe3a3, 0xe2f2, 0xe240 }; +#endif VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc4b1cccd, 0xc4a6b000, 0xc49b9333, 0xc4907667 }; @@ -50,6 +57,13 @@ void FNNAME (INSN_NAME) (void) DECL_VMUL(vector); DECL_VMUL(vector_res); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector, float, 16, 4); + DECL_VARIABLE(vector, float, 16, 8); + DECL_VARIABLE(vector_res, float, 16, 4); + DECL_VARIABLE(vector_res, float, 16, 8); +#endif + clean_results (); /* Initialize vector from pre-initialized values. */ @@ -57,11 +71,17 @@ void FNNAME (INSN_NAME) (void) VLOAD(vector, buffer, , int, s, 32, 2); VLOAD(vector, buffer, , uint, u, 16, 4); VLOAD(vector, buffer, , uint, u, 32, 2); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VLOAD(vector, buffer, , float, f, 16, 4); +#endif VLOAD(vector, buffer, , float, f, 32, 2); VLOAD(vector, buffer, q, int, s, 16, 8); VLOAD(vector, buffer, q, int, s, 32, 4); VLOAD(vector, buffer, q, uint, u, 16, 8); VLOAD(vector, buffer, q, uint, u, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VLOAD(vector, buffer, q, float, f, 16, 8); +#endif VLOAD(vector, buffer, q, float, f, 32, 4); /* Choose multiplier arbitrarily. */ @@ -69,22 +89,34 @@ void FNNAME (INSN_NAME) (void) TEST_VMUL_N(, int, s, 32, 2, 0x22); TEST_VMUL_N(, uint, u, 16, 4, 0x33); TEST_VMUL_N(, uint, u, 32, 2, 0x44); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VMUL_N(, float, f, 16, 4, 22.3f); +#endif TEST_VMUL_N(, float, f, 32, 2, 22.3f); TEST_VMUL_N(q, int, s, 16, 8, 0x55); TEST_VMUL_N(q, int, s, 32, 4, 0x66); TEST_VMUL_N(q, uint, u, 16, 8, 0x77); TEST_VMUL_N(q, uint, u, 32, 4, 0x88); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VMUL_N(q, float, f, 16, 8, 88.9f); +#endif TEST_VMUL_N(q, float, f, 32, 4, 88.9f); CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, ""); CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, ""); CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, ""); CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, ""); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, ""); +#endif CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, ""); CHECK(TEST_MSG, int, 16, 8, PRIx64, expected, ""); CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, ""); CHECK(TEST_MSG, uint, 16, 8, PRIx64, expected, ""); CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, ""); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, ""); +#endif CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, ""); } diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vneg.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vneg.c index 78f17ed155c..7bd9d555bdd 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vneg.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vneg.c @@ -21,24 +21,53 @@ VECT_VAR_DECL(expected,int,32,4) [] = { 0x10, 0xf, 0xe, 0xd }; /* Expected results for float32 variants. Needs to be separated since the generic test function does not test floating-point versions. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_float16, hfloat, 16, 4) [] = { 0xc09a, 0xc09a, + 0xc09a, 0xc09a }; +VECT_VAR_DECL(expected_float16, hfloat, 16, 8) [] = { 0xc2cd, 0xc2cd, + 0xc2cd, 0xc2cd, + 0xc2cd, 0xc2cd, + 0xc2cd, 0xc2cd }; +#endif VECT_VAR_DECL(expected_float32,hfloat,32,2) [] = { 0xc0133333, 0xc0133333 }; VECT_VAR_DECL(expected_float32,hfloat,32,4) [] = { 0xc059999a, 0xc059999a, 0xc059999a, 0xc059999a }; void exec_vneg_f32(void) { +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector, float, 16, 4); + DECL_VARIABLE(vector, float, 16, 8); +#endif DECL_VARIABLE(vector, float, 32, 2); DECL_VARIABLE(vector, float, 32, 4); + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector_res, float, 16, 4); + DECL_VARIABLE(vector_res, float, 16, 8); +#endif DECL_VARIABLE(vector_res, float, 32, 2); DECL_VARIABLE(vector_res, float, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector, , float, f, 16, 4, 2.3f); + VDUP(vector, q, float, f, 16, 8, 3.4f); +#endif VDUP(vector, , float, f, 32, 2, 2.3f); VDUP(vector, q, float, f, 32, 4, 3.4f); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_UNARY_OP(INSN_NAME, , float, f, 16, 4); + TEST_UNARY_OP(INSN_NAME, q, float, f, 16, 8); +#endif TEST_UNARY_OP(INSN_NAME, , float, f, 32, 2); TEST_UNARY_OP(INSN_NAME, q, float, f, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_float16, ""); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_float16, ""); +#endif CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_float32, ""); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_float32, ""); } diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc index c1b723526ba..a9b0c62c7e3 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc @@ -21,6 +21,9 @@ void FNNAME (INSN_NAME) (void) DECL_VARIABLE(vector, uint, 8, 8); DECL_VARIABLE(vector, uint, 16, 4); DECL_VARIABLE(vector, uint, 32, 2); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector, float, 16, 4); +#endif DECL_VARIABLE(vector, float, 32, 2); DECL_VARIABLE(vector_res, int, 8, 8); @@ -29,6 +32,9 @@ void FNNAME (INSN_NAME) (void) DECL_VARIABLE(vector_res, uint, 8, 8); DECL_VARIABLE(vector_res, uint, 16, 4); DECL_VARIABLE(vector_res, uint, 32, 2); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector_res, float, 16, 4); +#endif DECL_VARIABLE(vector_res, float, 32, 2); clean_results (); @@ -40,6 +46,9 @@ void FNNAME (INSN_NAME) (void) VLOAD(vector, buffer, , uint, u, 8, 8); VLOAD(vector, buffer, , uint, u, 16, 4); VLOAD(vector, buffer, , uint, u, 32, 2); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VLOAD(vector, buffer, , float, f, 16, 4); +#endif VLOAD(vector, buffer, , float, f, 32, 2); /* Apply a binary operator named INSN_NAME. */ @@ -49,6 +58,9 @@ void FNNAME (INSN_NAME) (void) TEST_VPXXX(INSN_NAME, uint, u, 8, 8); TEST_VPXXX(INSN_NAME, uint, u, 16, 4); TEST_VPXXX(INSN_NAME, uint, u, 32, 2); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VPXXX(INSN_NAME, float, f, 16, 4); +#endif TEST_VPXXX(INSN_NAME, float, f, 32, 2); CHECK(TEST_MSG, int, 8, 8, PRIx32, expected, ""); @@ -57,6 +69,9 @@ void FNNAME (INSN_NAME) (void) CHECK(TEST_MSG, uint, 8, 8, PRIx32, expected, ""); CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, ""); CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, ""); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, ""); +#endif CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, ""); } diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c index 5ddfd3d8456..f1bbe0964f9 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c @@ -14,6 +14,9 @@ VECT_VAR_DECL(expected,uint,8,8) [] = { 0xe1, 0xe5, 0xe9, 0xed, 0xe1, 0xe5, 0xe9, 0xed }; VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffe1, 0xffe5, 0xffe1, 0xffe5 }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffe1, 0xffffffe1 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xcfc0, 0xcec0, 0xcfc0, 0xcec0 }; +#endif VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1f80000, 0xc1f80000 }; #include "vpXXX.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c index f27a9a9ec59..c9621146a9a 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c @@ -15,6 +15,9 @@ VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7, 0xf1, 0xf3, 0xf5, 0xf7 }; VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff3, 0xfff1, 0xfff3 }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff1, 0xfffffff1 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xcb80, 0xca80, 0xcb80, 0xca80 }; +#endif VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1700000, 0xc1700000 }; #include "vpXXX.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c index a7cb6966c6e..7c75cf53988 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c @@ -15,6 +15,9 @@ VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6, 0xf0, 0xf2, 0xf4, 0xf6 }; VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff2, 0xfff0, 0xfff2 }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xcc00, 0xcb00, 0xcc00, 0xcb00 }; +#endif VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1800000 }; #include "vpXXX.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpe.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpe.c index 55b45b7a3b9..cd6a17f34b1 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpe.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpe.c @@ -7,6 +7,14 @@ VECT_VAR_DECL(expected_positive,uint,32,2) [] = { 0xffffffff, 0xffffffff }; VECT_VAR_DECL(expected_positive,uint,32,4) [] = { 0xbf000000, 0xbf000000, 0xbf000000, 0xbf000000 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_positive, hfloat, 16, 4) [] = { 0x3834, 0x3834, + 0x3834, 0x3834 }; +VECT_VAR_DECL(expected_positive, hfloat, 16, 8) [] = { 0x2018, 0x2018, + 0x2018, 0x2018, + 0x2018, 0x2018, + 0x2018, 0x2018 }; +#endif VECT_VAR_DECL(expected_positive,hfloat,32,2) [] = { 0x3f068000, 0x3f068000 }; VECT_VAR_DECL(expected_positive,hfloat,32,4) [] = { 0x3c030000, 0x3c030000, 0x3c030000, 0x3c030000 }; @@ -15,24 +23,56 @@ VECT_VAR_DECL(expected_positive,hfloat,32,4) [] = { 0x3c030000, 0x3c030000, VECT_VAR_DECL(expected_negative,uint,32,2) [] = { 0x80000000, 0x80000000 }; VECT_VAR_DECL(expected_negative,uint,32,4) [] = { 0xee800000, 0xee800000, 0xee800000, 0xee800000 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_negative, hfloat, 16, 4) [] = { 0xae64, 0xae64, + 0xae64, 0xae64 }; +VECT_VAR_DECL(expected_negative, hfloat, 16, 8) [] = { 0xa018, 0xa018, + 0xa018, 0xa018, + 0xa018, 0xa018, + 0xa018, 0xa018 }; +#endif VECT_VAR_DECL(expected_negative,hfloat,32,2) [] = { 0xbdcc8000, 0xbdcc8000 }; VECT_VAR_DECL(expected_negative,hfloat,32,4) [] = { 0xbc030000, 0xbc030000, 0xbc030000, 0xbc030000 }; /* Expected results with FP special values (NaN, infinity). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_fp1, hfloat, 16, 4) [] = { 0x7e00, 0x7e00, + 0x7e00, 0x7e00 }; +VECT_VAR_DECL(expected_fp1, hfloat, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0 }; +#endif VECT_VAR_DECL(expected_fp1,hfloat,32,2) [] = { 0x7fc00000, 0x7fc00000 }; VECT_VAR_DECL(expected_fp1,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 }; /* Expected results with FP special values (zero, large value). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_fp2, hfloat, 16, 4) [] = { 0x7c00, 0x7c00, + 0x7c00, 0x7c00 }; +VECT_VAR_DECL(expected_fp2, hfloat, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0 }; +#endif VECT_VAR_DECL(expected_fp2,hfloat,32,2) [] = { 0x7f800000, 0x7f800000 }; VECT_VAR_DECL(expected_fp2,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 }; /* Expected results with FP special values (-0, -infinity). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_fp3, hfloat, 16, 4) [] = { 0xfc00, 0xfc00, + 0xfc00, 0xfc00}; +VECT_VAR_DECL(expected_fp3, hfloat, 16, 8) [] = { 0x8000, 0x8000, + 0x8000, 0x8000, + 0x8000, 0x8000, + 0x8000, 0x8000 }; +#endif VECT_VAR_DECL(expected_fp3,hfloat,32,2) [] = { 0xff800000, 0xff800000 }; VECT_VAR_DECL(expected_fp3,hfloat,32,4) [] = { 0x80000000, 0x80000000, 0x80000000, 0x80000000 }; /* Expected results with FP special large negative value. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_fp4, hfloat, 16, 4) [] = { 0x8000, 0x8000, + 0x8000, 0x8000 }; +#endif VECT_VAR_DECL(expected_fp4,hfloat,32,2) [] = { 0x80000000, 0x80000000 }; #define TEST_MSG "VRECPE/VRECPEQ" @@ -50,11 +90,19 @@ void exec_vrecpe(void) /* No need for 64 bits variants. */ DECL_VARIABLE(vector, uint, 32, 2); DECL_VARIABLE(vector, uint, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector, float, 16, 4); + DECL_VARIABLE(vector, float, 16, 8); +#endif DECL_VARIABLE(vector, float, 32, 2); DECL_VARIABLE(vector, float, 32, 4); DECL_VARIABLE(vector_res, uint, 32, 2); DECL_VARIABLE(vector_res, uint, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector_res, float, 16, 4); + DECL_VARIABLE(vector_res, float, 16, 8); +#endif DECL_VARIABLE(vector_res, float, 32, 2); DECL_VARIABLE(vector_res, float, 32, 4); @@ -62,88 +110,165 @@ void exec_vrecpe(void) /* Choose init value arbitrarily, positive. */ VDUP(vector, , uint, u, 32, 2, 0x12345678); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector, , float, f, 16, 4, 1.9f); +#endif VDUP(vector, , float, f, 32, 2, 1.9f); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector, q, float, f, 16, 8, 125.0f); +#endif VDUP(vector, q, uint, u, 32, 4, 0xABCDEF10); VDUP(vector, q, float, f, 32, 4, 125.0f); /* Apply the operator. */ TEST_VRECPE(, uint, u, 32, 2); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VRECPE(, float, f, 16, 4); +#endif TEST_VRECPE(, float, f, 32, 2); TEST_VRECPE(q, uint, u, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VRECPE(q, float, f, 16, 8); +#endif TEST_VRECPE(q, float, f, 32, 4); #define CMT " (positive input)" CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_positive, CMT); CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_positive, CMT); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_positive, CMT); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_positive, CMT); +#endif CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_positive, CMT); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_positive, CMT); /* Choose init value arbitrarily,negative. */ VDUP(vector, , uint, u, 32, 2, 0xFFFFFFFF); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector, , float, f, 16, 4, -10.0f); +#endif VDUP(vector, , float, f, 32, 2, -10.0f); VDUP(vector, q, uint, u, 32, 4, 0x89081234); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector, q, float, f, 16, 8, -125.0f); +#endif VDUP(vector, q, float, f, 32, 4, -125.0f); /* Apply the operator. */ TEST_VRECPE(, uint, u, 32, 2); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VRECPE(, float, f, 16, 4); +#endif TEST_VRECPE(, float, f, 32, 2); TEST_VRECPE(q, uint, u, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VRECPE(q, float, f, 16, 8); +#endif TEST_VRECPE(q, float, f, 32, 4); #undef CMT #define CMT " (negative input)" CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_negative, CMT); CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_negative, CMT); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_negative, CMT); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_negative, CMT); +#endif CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_negative, CMT); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_negative, CMT); /* Test FP variants with special input values (NaN, infinity). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector, , float, f, 16, 4, NAN); + VDUP(vector, q, float, f, 16, 8, HUGE_VALF); +#endif VDUP(vector, , float, f, 32, 2, NAN); VDUP(vector, q, float, f, 32, 4, HUGE_VALF); /* Apply the operator. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VRECPE(, float, f, 16, 4); + TEST_VRECPE(q, float, f, 16, 8); +#endif TEST_VRECPE(, float, f, 32, 2); TEST_VRECPE(q, float, f, 32, 4); #undef CMT #define CMT " FP special (NaN, infinity)" +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp1, CMT); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp1, CMT); +#endif CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp1, CMT); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp1, CMT); /* Test FP variants with special input values (zero, large value). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector, , float, f, 16, 4, 0.0f); + VDUP(vector, q, float, f, 16, 8, 8.97229e37f /*9.0e37f*/); +#endif VDUP(vector, , float, f, 32, 2, 0.0f); VDUP(vector, q, float, f, 32, 4, 8.97229e37f /*9.0e37f*/); /* Apply the operator. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VRECPE(, float, f, 16, 4); + TEST_VRECPE(q, float, f, 16, 8); +#endif TEST_VRECPE(, float, f, 32, 2); TEST_VRECPE(q, float, f, 32, 4); #undef CMT #define CMT " FP special (zero, large value)" +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp2, CMT); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp2, CMT); +#endif CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp2, CMT); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp2, CMT); /* Test FP variants with special input values (-0, -infinity). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector, , float, f, 16, 4, -0.0f); + VDUP(vector, q, float, f, 16, 8, -HUGE_VALF); +#endif VDUP(vector, , float, f, 32, 2, -0.0f); VDUP(vector, q, float, f, 32, 4, -HUGE_VALF); /* Apply the operator. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VRECPE(, float, f, 16, 4); + TEST_VRECPE(q, float, f, 16, 8); +#endif TEST_VRECPE(, float, f, 32, 2); TEST_VRECPE(q, float, f, 32, 4); #undef CMT #define CMT " FP special (-0, -infinity)" +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp3, CMT); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp3, CMT); +#endif CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp3, CMT); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp3, CMT); /* Test FP variants with special input values (large negative value). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector, , float, f, 16, 4, -9.0e37f); +#endif VDUP(vector, , float, f, 32, 2, -9.0e37f); /* Apply the operator. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VRECPE(, float, f, 16, 4); +#endif TEST_VRECPE(, float, f, 32, 2); #undef CMT #define CMT " FP special (large negative value)" +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp4, CMT); +#endif CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp4, CMT); } diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecps.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecps.c index 0e41947f6d5..b06da223021 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecps.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecps.c @@ -4,22 +4,51 @@ #include /* Expected results with positive input. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xd70c, 0xd70c, 0xd70c, 0xd70c }; +VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xcedc, 0xcedc, 0xcedc, 0xcedc, + 0xcedc, 0xcedc, 0xcedc, 0xcedc }; +#endif VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc2e19eb7, 0xc2e19eb7 }; VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1db851f, 0xc1db851f, 0xc1db851f, 0xc1db851f }; /* Expected results with FP special values (NaN). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_fp1, hfloat, 16, 4) [] = { 0x7e00, 0x7e00, + 0x7e00, 0x7e00 }; +VECT_VAR_DECL(expected_fp1, hfloat, 16, 8) [] = { 0x7e00, 0x7e00, + 0x7e00, 0x7e00, + 0x7e00, 0x7e00, + 0x7e00, 0x7e00 }; +#endif VECT_VAR_DECL(expected_fp1,hfloat,32,2) [] = { 0x7fc00000, 0x7fc00000 }; VECT_VAR_DECL(expected_fp1,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000 }; /* Expected results with FP special values (infinity, 0) and normal values. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_fp2, hfloat, 16, 4) [] = { 0xfc00, 0xfc00, + 0xfc00, 0xfc00 }; +VECT_VAR_DECL(expected_fp2, hfloat, 16, 8) [] = { 0x4000, 0x4000, + 0x4000, 0x4000, + 0x4000, 0x4000, + 0x4000, 0x4000 }; +#endif VECT_VAR_DECL(expected_fp2,hfloat,32,2) [] = { 0xff800000, 0xff800000 }; VECT_VAR_DECL(expected_fp2,hfloat,32,4) [] = { 0x40000000, 0x40000000, 0x40000000, 0x40000000 }; /* Expected results with FP special values (infinity, 0). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_fp3, hfloat, 16, 4) [] = { 0x4000, 0x4000, + 0x4000, 0x4000 }; +VECT_VAR_DECL(expected_fp3, hfloat, 16, 8) [] = { 0x4000, 0x4000, + 0x4000, 0x4000, + 0x4000, 0x4000, + 0x4000, 0x4000 }; +#endif VECT_VAR_DECL(expected_fp3,hfloat,32,2) [] = { 0x40000000, 0x40000000 }; VECT_VAR_DECL(expected_fp3,hfloat,32,4) [] = { 0x40000000, 0x40000000, 0x40000000, 0x40000000 }; @@ -38,74 +67,143 @@ void exec_vrecps(void) VECT_VAR(vector_res, T1, W, N)) /* No need for integer variants. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector, float, 16, 4); + DECL_VARIABLE(vector, float, 16, 8); +#endif DECL_VARIABLE(vector, float, 32, 2); DECL_VARIABLE(vector, float, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector2, float, 16, 4); + DECL_VARIABLE(vector2, float, 16, 8); +#endif DECL_VARIABLE(vector2, float, 32, 2); DECL_VARIABLE(vector2, float, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector_res, float, 16, 4); + DECL_VARIABLE(vector_res, float, 16, 8); +#endif DECL_VARIABLE(vector_res, float, 32, 2); DECL_VARIABLE(vector_res, float, 32, 4); clean_results (); /* Choose init value arbitrarily. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector, , float, f, 16, 4, 12.9f); + VDUP(vector, q, float, f, 16, 8, 9.2f); +#endif VDUP(vector, , float, f, 32, 2, 12.9f); VDUP(vector, q, float, f, 32, 4, 9.2f); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector2, , float, f, 16, 4, 8.9f); + VDUP(vector2, q, float, f, 16, 8, 3.2f); +#endif VDUP(vector2, , float, f, 32, 2, 8.9f); VDUP(vector2, q, float, f, 32, 4, 3.2f); /* Apply the operator. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VRECPS(, float, f, 16, 4); + TEST_VRECPS(q, float, f, 16, 8); +#endif TEST_VRECPS(, float, f, 32, 2); TEST_VRECPS(q, float, f, 32, 4); #define CMT " (positive input)" +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, CMT); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, CMT); +#endif CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, CMT); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, CMT); /* Test FP variants with special input values (NaN). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector, , float, f, 16, 4, NAN); + VDUP(vector2, q, float, f, 16, 8, NAN); +#endif VDUP(vector, , float, f, 32, 2, NAN); VDUP(vector2, q, float, f, 32, 4, NAN); /* Apply the operator. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VRECPS(, float, f, 16, 4); + TEST_VRECPS(q, float, f, 16, 8); +#endif TEST_VRECPS(, float, f, 32, 2); TEST_VRECPS(q, float, f, 32, 4); #undef CMT #define CMT " FP special (NaN)" +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp1, CMT); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp1, CMT); +#endif CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp1, CMT); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp1, CMT); /* Test FP variants with special input values (infinity, 0). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector, , float, f, 16, 4, HUGE_VALF); + VDUP(vector, q, float, f, 16, 8, 0.0f); + VDUP(vector2, q, float, f, 16, 8, 3.2f); /* Restore a normal value. */ +#endif VDUP(vector, , float, f, 32, 2, HUGE_VALF); VDUP(vector, q, float, f, 32, 4, 0.0f); VDUP(vector2, q, float, f, 32, 4, 3.2f); /* Restore a normal value. */ + /* Apply the operator. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VRECPS(, float, f, 16, 4); + TEST_VRECPS(q, float, f, 16, 8); +#endif TEST_VRECPS(, float, f, 32, 2); TEST_VRECPS(q, float, f, 32, 4); #undef CMT #define CMT " FP special (infinity, 0) and normal value" +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp2, CMT); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp2, CMT); +#endif CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp2, CMT); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp2, CMT); /* Test FP variants with only special input values (infinity, 0). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector, , float, f, 16, 4, HUGE_VALF); + VDUP(vector, q, float, f, 16, 8, 0.0f); + VDUP(vector2, , float, f, 16, 4, 0.0f); + VDUP(vector2, q, float, f, 16, 8, HUGE_VALF); +#endif VDUP(vector, , float, f, 32, 2, HUGE_VALF); VDUP(vector, q, float, f, 32, 4, 0.0f); VDUP(vector2, , float, f, 32, 2, 0.0f); VDUP(vector2, q, float, f, 32, 4, HUGE_VALF); + /* Apply the operator */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VRECPS(, float, f, 16, 4); + TEST_VRECPS(q, float, f, 16, 8); +#endif TEST_VRECPS(, float, f, 32, 2); TEST_VRECPS(q, float, f, 32, 4); #undef CMT #define CMT " FP special (infinity, 0)" +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp3, CMT); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp3, CMT); +#endif CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp3, CMT); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp3, CMT); } diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c index d97a3a25ee5..fe6715f3cee 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c @@ -6,6 +6,14 @@ #include "compute-ref-data.h" /* Expected results. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0xcb80, + 0xcb00, 0xca80 }; +VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb80, + 0xcb00, 0xca80, + 0xca00, 0xc980, + 0xc900, 0xc880 }; +#endif VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 }; VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000, 0xc1600000, 0xc1500000 }; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc index 629240d3a23..bb4a6ba442a 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc @@ -17,20 +17,40 @@ void FNNAME (INSN) (void) #define TEST_VRND(Q, T1, T2, W, N) \ TEST_VRND1 (INSN, Q, T1, T2, W, N) +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector, float, 16, 4); + DECL_VARIABLE(vector, float, 16, 8); +#endif DECL_VARIABLE (vector, float, 32, 2); DECL_VARIABLE (vector, float, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector_res, float, 16, 4); + DECL_VARIABLE(vector_res, float, 16, 8); +#endif DECL_VARIABLE (vector_res, float, 32, 2); DECL_VARIABLE (vector_res, float, 32, 4); clean_results (); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VLOAD (vector, buffer, , float, f, 16, 4); + VLOAD (vector, buffer, q, float, f, 16, 8); +#endif VLOAD (vector, buffer, , float, f, 32, 2); VLOAD (vector, buffer, q, float, f, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VRND ( , float, f, 16, 4); + TEST_VRND (q, float, f, 16, 8); +#endif TEST_VRND ( , float, f, 32, 2); TEST_VRND (q, float, f, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected, ""); + CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected, ""); +#endif CHECK_FP (TEST_MSG, float, 32, 2, PRIx32, expected, ""); CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected, ""); } diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c index ff2bdc0563f..9c0f7ffcf38 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c @@ -6,6 +6,15 @@ #include "compute-ref-data.h" /* Expected results. */ +/* Expected results. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0xcb80, + 0xcb00, 0xca80 }; +VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb80, + 0xcb00, 0xca80, + 0xca00, 0xc980, + 0xc900, 0xc880 }; +#endif VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 }; VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000, 0xc1600000, 0xc1500000 }; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c index eae9f61c585..9bfaffceaeb 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c @@ -6,6 +6,15 @@ #include "compute-ref-data.h" /* Expected results. */ +/* Expected results. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0xcb80, + 0xcb00, 0xca80 }; +VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb80, + 0xcb00, 0xca80, + 0xca00, 0xc980, + 0xc900, 0xc880 }; +#endif VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 }; VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000, 0xc1600000, 0xc1500000 }; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c index c6c707d6765..52b99424d28 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c @@ -6,6 +6,15 @@ #include "compute-ref-data.h" /* Expected results. */ +/* Expected results. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0xcb80, + 0xcb00, 0xca80 }; +VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb80, + 0xcb00, 0xca80, + 0xca00, 0xc980, + 0xc900, 0xc880 }; +#endif VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 }; VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000, 0xc1600000, 0xc1500000 }; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c index e94eb6b7622..2e888b9caf6 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c @@ -6,6 +6,14 @@ #include "compute-ref-data.h" /* Expected results. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0xcb80, + 0xcb00, 0xca80 }; +VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb80, + 0xcb00, 0xca80, + 0xca00, 0xc980, + 0xc900, 0xc880 }; +#endif VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 }; VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000, 0xc1600000, 0xc1500000 }; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c index 0d2a63ef26c..400ddf84f9b 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c @@ -6,6 +6,14 @@ #include "compute-ref-data.h" /* Expected results. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0xcb80, + 0xcb00, 0xca80 }; +VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb80, + 0xcb00, 0xca80, + 0xca00, 0xc980, + 0xc900, 0xc880 }; +#endif VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 }; VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000, 0xc1600000, 0xc1500000 }; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c index 0291ec00c5e..77e221023c4 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c @@ -7,6 +7,11 @@ VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffff, 0xffffffff }; VECT_VAR_DECL(expected,uint,32,4) [] = { 0x9c800000, 0x9c800000, 0x9c800000, 0x9c800000 }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0x324c, 0x324c, 0x324c, 0x324c }; +VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0x3380, 0x3380, 0x3380, 0x3380, + 0x3380, 0x3380, 0x3380, 0x3380 }; +#endif VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x3e498000, 0x3e498000 }; VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x3e700000, 0x3e700000, 0x3e700000, 0x3e700000 }; @@ -22,17 +27,39 @@ VECT_VAR_DECL(expected_2,uint,32,4) [] = { 0xed000000, 0xed000000, 0xed000000, 0xed000000 }; /* Expected results with FP special inputs values (NaNs, ...). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_fp1, hfloat, 16, 4) [] = { 0x7e00, 0x7e00, + 0x7e00, 0x7e00 }; +VECT_VAR_DECL(expected_fp1, hfloat, 16, 8) [] = { 0x7c00, 0x7c00, + 0x7c00, 0x7c00, + 0x7c00, 0x7c00, + 0x7c00, 0x7c00 }; +#endif VECT_VAR_DECL(expected_fp1,hfloat,32,2) [] = { 0x7fc00000, 0x7fc00000 }; VECT_VAR_DECL(expected_fp1,hfloat,32,4) [] = { 0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000 }; /* Expected results with FP special inputs values (negative, infinity). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_fp2, hfloat, 16, 4) [] = { 0x7e00, 0x7e00, + 0x7e00, 0x7e00 }; +VECT_VAR_DECL(expected_fp2, hfloat, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0 }; +#endif VECT_VAR_DECL(expected_fp2,hfloat,32,2) [] = { 0x7fc00000, 0x7fc00000 }; VECT_VAR_DECL(expected_fp2,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 }; /* Expected results with FP special inputs values (-0, -infinity). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_fp3, hfloat, 16, 4) [] = { 0xfc00, 0xfc00, + 0xfc00, 0xfc00 }; +VECT_VAR_DECL(expected_fp3, hfloat, 16, 8) [] = { 0x7e00, 0x7e00, + 0x7e00, 0x7e00, + 0x7e00, 0x7e00, + 0x7e00, 0x7e00 }; +#endif VECT_VAR_DECL(expected_fp3,hfloat,32,2) [] = { 0xff800000, 0xff800000 }; VECT_VAR_DECL(expected_fp3,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000 }; @@ -50,32 +77,60 @@ void exec_vrsqrte(void) VECT_VAR(vector_res, T1, W, N)) DECL_VARIABLE(vector, uint, 32, 2); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector, float, 16, 4); +#endif DECL_VARIABLE(vector, float, 32, 2); DECL_VARIABLE(vector, uint, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector, float, 16, 8); +#endif DECL_VARIABLE(vector, float, 32, 4); DECL_VARIABLE(vector_res, uint, 32, 2); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector_res, float, 16, 4); +#endif DECL_VARIABLE(vector_res, float, 32, 2); DECL_VARIABLE(vector_res, uint, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector_res, float, 16, 8); +#endif DECL_VARIABLE(vector_res, float, 32, 4); clean_results (); /* Choose init value arbitrarily. */ VDUP(vector, , uint, u, 32, 2, 0x12345678); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector, , float, f, 16, 4, 25.799999f); +#endif VDUP(vector, , float, f, 32, 2, 25.799999f); VDUP(vector, q, uint, u, 32, 4, 0xABCDEF10); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector, q, float, f, 16, 8, 18.2f); +#endif VDUP(vector, q, float, f, 32, 4, 18.2f); /* Apply the operator. */ TEST_VRSQRTE(, uint, u, 32, 2); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VRSQRTE(, float, f, 16, 4); +#endif TEST_VRSQRTE(, float, f, 32, 2); TEST_VRSQRTE(q, uint, u, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VRSQRTE(q, float, f, 16, 8); +#endif TEST_VRSQRTE(q, float, f, 32, 4); #define CMT "" CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, CMT); CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, CMT); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, CMT); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, CMT); +#endif CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, CMT); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, CMT); @@ -110,42 +165,78 @@ void exec_vrsqrte(void) /* Test FP variants with special input values (NaNs, ...). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector, , float, f, 16, 4, NAN); + VDUP(vector, q, float, f, 16, 8, 0.0f); +#endif VDUP(vector, , float, f, 32, 2, NAN); VDUP(vector, q, float, f, 32, 4, 0.0f); /* Apply the operator. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VRSQRTE(, float, f, 16, 4); + TEST_VRSQRTE(q, float, f, 16, 8); +#endif TEST_VRSQRTE(, float, f, 32, 2); TEST_VRSQRTE(q, float, f, 32, 4); #undef CMT #define CMT " FP special (NaN, 0)" +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp1, CMT); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp1, CMT); +#endif CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp1, CMT); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp1, CMT); /* Test FP variants with special input values (negative, infinity). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector, , float, f, 16, 4, -1.0f); + VDUP(vector, q, float, f, 16, 8, HUGE_VALF); +#endif VDUP(vector, , float, f, 32, 2, -1.0f); VDUP(vector, q, float, f, 32, 4, HUGE_VALF); /* Apply the operator. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VRSQRTE(, float, f, 16, 4); + TEST_VRSQRTE(q, float, f, 16, 8); +#endif TEST_VRSQRTE(, float, f, 32, 2); TEST_VRSQRTE(q, float, f, 32, 4); #undef CMT #define CMT " FP special (negative, infinity)" +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp2, CMT); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp2, CMT); +#endif CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp2, CMT); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp2, CMT); /* Test FP variants with special input values (-0, -infinity). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector, , float, f, 16, 4, -0.0f); + VDUP(vector, q, float, f, 16, 8, -HUGE_VALF); +#endif VDUP(vector, , float, f, 32, 2, -0.0f); VDUP(vector, q, float, f, 32, 4, -HUGE_VALF); /* Apply the operator. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VRSQRTE(, float, f, 16, 4); + TEST_VRSQRTE(q, float, f, 16, 8); +#endif TEST_VRSQRTE(, float, f, 32, 2); TEST_VRSQRTE(q, float, f, 32, 4); #undef CMT #define CMT " FP special (-0, -infinity)" +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp3, CMT); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp3, CMT); +#endif CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp3, CMT); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp3, CMT); } diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c index 4531026dc4c..06626e40885 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c @@ -4,22 +4,51 @@ #include /* Expected results. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xd3cb, 0xd3cb, 0xd3cb, 0xd3cb }; +VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xc726, 0xc726, 0xc726, 0xc726, + 0xc726, 0xc726, 0xc726, 0xc726 }; +#endif VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc2796b84, 0xc2796b84 }; VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc0e4a3d8, 0xc0e4a3d8, 0xc0e4a3d8, 0xc0e4a3d8 }; /* Expected results with input=NaN. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_nan, hfloat, 16, 4) [] = { 0x7e00, 0x7e00, + 0x7e00, 0x7e00 }; +VECT_VAR_DECL(expected_nan, hfloat, 16, 8) [] = { 0x7e00, 0x7e00, + 0x7e00, 0x7e00, + 0x7e00, 0x7e00, + 0x7e00, 0x7e00 }; +#endif VECT_VAR_DECL(expected_nan,hfloat,32,2) [] = { 0x7fc00000, 0x7fc00000 }; VECT_VAR_DECL(expected_nan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000 }; /* Expected results with FP special inputs values (infinity, 0). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_fp1, hfloat, 16, 4) [] = { 0xfc00, 0xfc00, + 0xfc00, 0xfc00 }; +VECT_VAR_DECL(expected_fp1, hfloat, 16, 8) [] = { 0x3e00, 0x3e00, + 0x3e00, 0x3e00, + 0x3e00, 0x3e00, + 0x3e00, 0x3e00 }; +#endif VECT_VAR_DECL(expected_fp1,hfloat,32,2) [] = { 0xff800000, 0xff800000 }; VECT_VAR_DECL(expected_fp1,hfloat,32,4) [] = { 0x3fc00000, 0x3fc00000, 0x3fc00000, 0x3fc00000 }; /* Expected results with only FP special inputs values (infinity, 0). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_fp2, hfloat, 16, 4) [] = { 0x3e00, 0x3e00, + 0x3e00, 0x3e00 }; +VECT_VAR_DECL(expected_fp2, hfloat, 16, 8) [] = { 0x3e00, 0x3e00, + 0x3e00, 0x3e00, + 0x3e00, 0x3e00, + 0x3e00, 0x3e00 }; +#endif VECT_VAR_DECL(expected_fp2,hfloat,32,2) [] = { 0x3fc00000, 0x3fc00000 }; VECT_VAR_DECL(expected_fp2,hfloat,32,4) [] = { 0x3fc00000, 0x3fc00000, 0x3fc00000, 0x3fc00000 }; @@ -38,75 +67,143 @@ void exec_vrsqrts(void) VECT_VAR(vector_res, T1, W, N)) /* No need for integer variants. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector, float, 16, 4); + DECL_VARIABLE(vector, float, 16, 8); +#endif DECL_VARIABLE(vector, float, 32, 2); DECL_VARIABLE(vector, float, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector2, float, 16, 4); + DECL_VARIABLE(vector2, float, 16, 8); +#endif DECL_VARIABLE(vector2, float, 32, 2); DECL_VARIABLE(vector2, float, 32, 4); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector_res, float, 16, 4); + DECL_VARIABLE(vector_res, float, 16, 8); +#endif DECL_VARIABLE(vector_res, float, 32, 2); DECL_VARIABLE(vector_res, float, 32, 4); clean_results (); /* Choose init value arbitrarily. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector, , float, f, 16, 4, 12.9f); + VDUP(vector, q, float, f, 16, 8, 9.1f); +#endif VDUP(vector, , float, f, 32, 2, 12.9f); VDUP(vector, q, float, f, 32, 4, 9.1f); +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector2, , float, f, 16, 4, 9.9f); + VDUP(vector2, q, float, f, 16, 8, 1.9f); +#endif VDUP(vector2, , float, f, 32, 2, 9.9f); VDUP(vector2, q, float, f, 32, 4, 1.9f); /* Apply the operator. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VRSQRTS(, float, f, 16, 4); + TEST_VRSQRTS(q, float, f, 16, 8); +#endif TEST_VRSQRTS(, float, f, 32, 2); TEST_VRSQRTS(q, float, f, 32, 4); #define CMT "" +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, CMT); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, CMT); +#endif CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, CMT); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, CMT); /* Test FP variants with special input values (NaN). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector, , float, f, 16, 4, NAN); + VDUP(vector2, q, float, f, 16, 8, NAN); +#endif VDUP(vector, , float, f, 32, 2, NAN); VDUP(vector2, q, float, f, 32, 4, NAN); /* Apply the operator. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VRSQRTS(, float, f, 16, 4); + TEST_VRSQRTS(q, float, f, 16, 8); +#endif TEST_VRSQRTS(, float, f, 32, 2); TEST_VRSQRTS(q, float, f, 32, 4); #undef CMT #define CMT " FP special (NAN) and normal values" +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_nan, CMT); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_nan, CMT); +#endif CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_nan, CMT); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_nan, CMT); /* Test FP variants with special input values (infinity, 0). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector, , float, f, 16, 4, HUGE_VALF); + VDUP(vector, q, float, f, 16, 8, 0.0f); + /* Restore a normal value in vector2. */ + VDUP(vector2, q, float, f, 16, 8, 3.2f); +#endif VDUP(vector, , float, f, 32, 2, HUGE_VALF); VDUP(vector, q, float, f, 32, 4, 0.0f); /* Restore a normal value in vector2. */ VDUP(vector2, q, float, f, 32, 4, 3.2f); /* Apply the operator. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VRSQRTS(, float, f, 16, 4); + TEST_VRSQRTS(q, float, f, 16, 8); +#endif TEST_VRSQRTS(, float, f, 32, 2); TEST_VRSQRTS(q, float, f, 32, 4); #undef CMT #define CMT " FP special (infinity, 0) and normal values" +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp1, CMT); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp1, CMT); +#endif CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp1, CMT); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp1, CMT); /* Test FP variants with only special input values (infinity, 0). */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + VDUP(vector, , float, f, 16, 4, HUGE_VALF); + VDUP(vector, q, float, f, 16, 8, 0.0f); + VDUP(vector2, , float, f, 16, 4, -0.0f); + VDUP(vector2, q, float, f, 16, 8, HUGE_VALF); +#endif VDUP(vector, , float, f, 32, 2, HUGE_VALF); VDUP(vector, q, float, f, 32, 4, 0.0f); VDUP(vector2, , float, f, 32, 2, -0.0f); VDUP(vector2, q, float, f, 32, 4, HUGE_VALF); /* Apply the operator. */ +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + TEST_VRSQRTS(, float, f, 16, 4); + TEST_VRSQRTS(q, float, f, 16, 8); +#endif TEST_VRSQRTS(, float, f, 32, 2); TEST_VRSQRTS(q, float, f, 32, 4); #undef CMT #define CMT " only FP special (infinity, 0)" +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp2, CMT); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp2, CMT); +#endif CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp2, CMT); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp2, CMT); } diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsub.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsub.c index 1a108d5110f..19d1fd2270b 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsub.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsub.c @@ -44,6 +44,14 @@ VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffffffffffed, VECT_VAR_DECL(expected_float32,hfloat,32,2) [] = { 0xc00ccccd, 0xc00ccccd }; VECT_VAR_DECL(expected_float32,hfloat,32,4) [] = { 0xc00ccccc, 0xc00ccccc, 0xc00ccccc, 0xc00ccccc }; +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +VECT_VAR_DECL(expected_float16, hfloat, 16, 4) [] = { 0xc066, 0xc066, + 0xc066, 0xc066 }; +VECT_VAR_DECL(expected_float16, hfloat, 16, 8) [] = { 0xc067, 0xc067, + 0xc067, 0xc067, + 0xc067, 0xc067, + 0xc067, 0xc067 }; +#endif void exec_vsub_f32(void) { @@ -67,4 +75,27 @@ void exec_vsub_f32(void) CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_float32, ""); CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_float32, ""); + +#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + DECL_VARIABLE(vector, float, 16, 4); + DECL_VARIABLE(vector, float, 16, 8); + + DECL_VARIABLE(vector2, float, 16, 4); + DECL_VARIABLE(vector2, float, 16, 8); + + DECL_VARIABLE(vector_res, float, 16, 4); + DECL_VARIABLE(vector_res, float, 16, 8); + + VDUP(vector, , float, f, 16, 4, 2.3f); + VDUP(vector, q, float, f, 16, 8, 3.4f); + + VDUP(vector2, , float, f, 16, 4, 4.5f); + VDUP(vector2, q, float, f, 16, 8, 5.6f); + + TEST_BINARY_OP(INSN_NAME, , float, f, 16, 4); + TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8); + + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_float16, ""); + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_float16, ""); +#endif } -- 2.30.2