From caba5478fd9cf3ade106e0b3de829326592eaf87 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 11 Oct 2022 15:17:45 +0100
Subject: [PATCH] add sv.stwu/pi example in test_sv_load_store_postinc

---
 openpower/isa/pifixedstore.mdwn               | 18 +++++++++---------
 .../decoder/isa/test_caller_svp64_ldst.py     | 19 ++++++++++---------
 src/openpower/sv/trans/test_pysvp64dis.py     |  1 +
 3 files changed, 20 insertions(+), 18 deletions(-)

diff --git a/openpower/isa/pifixedstore.mdwn b/openpower/isa/pifixedstore.mdwn
index a8060e56..0181de11 100644
--- a/openpower/isa/pifixedstore.mdwn
+++ b/openpower/isa/pifixedstore.mdwn
@@ -7,7 +7,7 @@
 
 D-Form
 
-* stbu RS,D(RA)
+* stbup RS,D(RA)
 
 Pseudo-code:
 
@@ -24,7 +24,7 @@ Special Registers Altered:
 
 X-Form
 
-* stbux RS,RA,RB
+* stbupx RS,RA,RB
 
 Pseudo-code:
 
@@ -41,7 +41,7 @@ Special Registers Altered:
 
 D-Form
 
-* sthu RS,D(RA)
+* sthup RS,D(RA)
 
 Pseudo-code:
 
@@ -58,7 +58,7 @@ Special Registers Altered:
 
 X-Form
 
-* sthux RS,RA,RB
+* sthupx RS,RA,RB
 
 Pseudo-code:
 
@@ -75,7 +75,7 @@ Special Registers Altered:
 
 D-Form
 
-* stwu RS,D(RA)
+* stwup RS,D(RA)
 
 Pseudo-code:
 
@@ -92,7 +92,7 @@ Special Registers Altered:
 
 X-Form
 
-* stwux RS,RA,RB
+* stwupx RS,RA,RB
 
 Pseudo-code:
 
@@ -109,13 +109,13 @@ Special Registers Altered:
 
 DS-Form
 
-* stdu RS,DS(RA)
+* stdup RS,DS(RA)
 
 Pseudo-code:
 
     EA <- (RA) + EXTS(DS || 0b00)
     ea <- (RA)
-    MEM(ea, 8) <- (RS)
+    MEM(EA, 8) <- (RS)
     RA <- EA
 
 Special Registers Altered:
@@ -126,7 +126,7 @@ Special Registers Altered:
 
 X-Form
 
-* stdux RS,RA,RB
+* stdupx RS,RA,RB
 
 Pseudo-code:
 
diff --git a/src/openpower/decoder/isa/test_caller_svp64_ldst.py b/src/openpower/decoder/isa/test_caller_svp64_ldst.py
index bed62b8c..f98ff5d5 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_ldst.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_ldst.py
@@ -30,13 +30,12 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.fpr(i), SelectableInt(expected[i], 64))
 
     def test_sv_load_store_postinc(self):
-        """>>> lst = ["addi 2, 0, 0x0010",
+        """>>> lst = ["addi 20, 0, 0x0010",
                         "addi 3, 0, 0x0008",
                         "addi 4, 0, 0x1234",
                         "addi 5, 0, 0x1235",
-                        "sv.stw/els *4, 24(2)",
-                        "addi 2, 2, 24",   # add on the 24
-                        "sv.lwu/pi *8, 8(2)"]
+                        "sv.stwu/pi *4, 24(20)",
+                        "sv.lwu/pi *8, 24(20)"]
 
         element stride is computed as:
         for i in range(VL):
@@ -54,14 +53,14 @@ class DecoderTestCase(FHDLTestCase):
             *vector = MEM(EA)
             RA = EA # still updated after but it's used before
         """
-        lst = SVP64Asm(["addi 2, 0, 0x0010",
+        lst = SVP64Asm(["addi 20, 0, 0x0010",
+                        "addi 22, 0, 0x0010",
                         "addi 3, 0, 0x0008",
                         "addi 4, 0, 0x1234",
                         "addi 5, 0, 0x1235",
-                        "sv.stw/els *4, 24(2)",  # scalar r1 + 16 + 24*offs
-                        "addi 20, 2, 0",   # copy 2 to 20
-                        "sv.lwzu/pi *8, 24(20)"
-                        ]) # scalar r1 + 24*offs
+                        "sv.stwu/pi *4, 24(22)",  # scalar r22 += 24 on update
+                        "sv.lwzu/pi *8, 24(20)"   # scalar r20 += 24 on update
+                        ])
         lst = list(lst)
 
         # SVSTATE (in this case, VL=2)
@@ -88,6 +87,8 @@ class DecoderTestCase(FHDLTestCase):
             # reg 20 (the EA) is expected to be the initial 16,
             # plus 2x24 (2 lots of immediates).  16+2*24=64
             self.assertEqual(sim.gpr(20), SelectableInt(64, 64))
+            # likewise, reg 22 - for the store - also 16+2*24.
+            self.assertEqual(sim.gpr(22), SelectableInt(64, 64))
 
     def test_sv_load_store_elementstride(self):
         """>>> lst = ["addi 2, 0, 0x0010",
diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index 9621a447..9e30fd46 100644
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -389,6 +389,7 @@ class SVSTATETestCase(unittest.TestCase):
                     "sv.ldu/pi 5,8(2)",
                     "sv.lwzu/pi *6,8(2)",
                     "sv.lwzu/pi *6,24(2)",
+                    "sv.stwu/pi *6,24(2)",
                         ]
         self._do_tst(expected)
 
-- 
2.30.2