From cacda621f3e21a68c910bf22a339c88217f28f39 Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 21 Dec 2020 13:45:09 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64.mdwn | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index 6358b5e1e..4b9022883 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -67,7 +67,8 @@ RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers. This is ## Future expansion. With the way that EXTRA fields are defined and applied to register fields, -future versions of SV may involve 256 or greater registers. To accommodate 256 registers, numbering of Vectors will simply shift up by one bit. Backwards bibary compatibility may be achieved with a PCR bit. Beyond this, further discussion is out of scope for this version of svp64. +future versions of SV may involve 256 or greater registers. To accommodate 256 registers, numbering of Vectors will simply shift up by one bit, without +requiring additional prefix bits. Backwards binary compatibility may be achieved with a PCR bit (Program Compatibility Register). Beyond this, further discussion is out of scope for this version of svp64. # Remapped Encoding (`RM[0:23]`) -- 2.30.2