From cacefd0a29d565575c5bf3db21e21c1bbba668bb Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 15 Jun 2018 11:31:53 +0100
Subject: [PATCH] add extra image slides

---
 pinmux/pinmux_chennai_2018.tex | 35 ++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/pinmux/pinmux_chennai_2018.tex b/pinmux/pinmux_chennai_2018.tex
index 3ba946ee2..94b9320a4 100644
--- a/pinmux/pinmux_chennai_2018.tex
+++ b/pinmux/pinmux_chennai_2018.tex
@@ -56,6 +56,41 @@
 }
 
 
+\frame{\frametitle{Simplified I/O pad Block Diagram}
+ \begin{center}
+  \includegraphics[height=2.5in]{reg_gpio_pinblock.jpg}\\
+  {\bf 3 wires: IN, OUT, OUTEN (also = !INEN) }
+ \end{center}
+}
+
+
+\frame{\frametitle{Output (and OUTEN) Wiring. 2 pins, 2 GPIO, 2 Fns}
+ \begin{center}
+  \includegraphics[height=2.5in]{reg_gpio_out_wiring.jpg}\\
+  {\bf Reg0 for Pin0, Reg1 for Pin1, Output and OUTEN same mux }
+ \end{center}
+}
+
+
+\frame{\frametitle{Input Selection and Priority Muxing}
+ \begin{center}
+  \includegraphics[height=0.75in]{reg_gpio_comparator.jpg}\\
+  {\bf Muxer enables input selection}\\
+  \vspace{10pt}
+  \includegraphics[height=1.25in]{reg_gpio_in_prioritymux.jpg}\\
+  {\bf However multiple inputs must be prioritised }
+ \end{center}
+}
+
+
+\frame{\frametitle{Input Mux Wiring}
+ \begin{center}
+  \includegraphics[height=2.5in]{reg_gpio_in_wiring.jpg}\\
+  {\bf Pin Mux selection vals NOT same as FN selection vals}
+ \end{center}
+}
+
+
 \frame{\frametitle{Summary}
 
  \begin{itemize}
-- 
2.30.2