From cad40fc87449e69a086a627bfb25aa49ae400753 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 22 Aug 2016 14:26:33 +0200 Subject: [PATCH] Fixed bug in memory_share for memory ports with different ABITS --- passes/memory/memory_share.cc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index f298169de..bcb7433a2 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -619,6 +619,12 @@ struct MemoryShareWorker RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en); + if (GetSize(last_addr) < GetSize(this_addr)) + last_addr.extend_u0(GetSize(this_addr)); + else + this_addr.extend_u0(GetSize(last_addr)); + + wr_ports[i]->setParam("\\ABITS", GetSize(this_addr)); wr_ports[i]->setPort("\\ADDR", module->Mux(NEW_ID, last_addr, this_addr, this_en_active)); wr_ports[i]->setPort("\\DATA", module->Mux(NEW_ID, last_data, this_data, this_en_active)); -- 2.30.2