From cadaa5224a27a03e954df59576f41d0f6b75a443 Mon Sep 17 00:00:00 2001 From: "Frank Ch. Eigler" Date: Tue, 5 Feb 2002 19:40:45 +0000 Subject: [PATCH] * opcodes disassembler extension [includes] 2002-02-04 Frank Ch. Eigler * dis-asm.h (disassemble_info): New field `insn_sets'. (INIT_DISASSEMBLE_INFO): Clear it. [opcodes] 2002-02-04 Frank Ch. Eigler * cgen-dis.in (print_insn_@arch@): Support disassemble_info.insn_sets. --- include/ChangeLog | 5 +++++ include/dis-asm.h | 6 ++++++ opcodes/ChangeLog | 4 ++++ opcodes/cgen-dis.in | 2 +- 4 files changed, 16 insertions(+), 1 deletion(-) diff --git a/include/ChangeLog b/include/ChangeLog index 9ac65a039bc..e482f97bb14 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,8 @@ +2002-02-05 Frank Ch. Eigler + + * dis-asm.h (disassemble_info): New field `insn_sets'. + (INIT_DISASSEMBLE_INFO): Clear it. + 2002-02-05 Jason Merrill * demangle.h (cplus_demangle_v3): Add "options" parm. diff --git a/include/dis-asm.h b/include/dis-asm.h index 8cd848dbd39..5b9e390d34c 100644 --- a/include/dis-asm.h +++ b/include/dis-asm.h @@ -73,6 +73,11 @@ typedef struct disassemble_info { unsigned long mach; /* Endianness (for bi-endian cpus). Mono-endian cpus can ignore this. */ enum bfd_endian endian; + /* An arch/mach-specific bitmask of selected instruction subsets, mainly + for processors with run-time-switchable instruction sets. The default, + zero, means that there is no constraint. CGEN-based opcodes ports + may use ISA_foo masks. */ + unsigned long insn_sets; /* Some targets need information about the current section to accurately display insns. If this is NULL, the target disassembler function @@ -275,6 +280,7 @@ extern int generic_symbol_at_address (INFO).flavour = bfd_target_unknown_flavour, \ (INFO).arch = bfd_arch_unknown, \ (INFO).mach = 0, \ + (INFO).insn_sets = 0, \ (INFO).endian = BFD_ENDIAN_UNKNOWN, \ (INFO).octets_per_byte = 1, \ INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 3230a495db4..745448456a8 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2002-02-04 Frank Ch. Eigler + + * cgen-dis.in (print_insn_@arch@): Support disassemble_info.insn_sets. + 2002-02-04 Alexandre Oliva * sh-opc.h (sh_arg_type): Added A_DISP_PC_ABS. diff --git a/opcodes/cgen-dis.in b/opcodes/cgen-dis.in index f2c9dd54ce3..c78723e2641 100644 --- a/opcodes/cgen-dis.in +++ b/opcodes/cgen-dis.in @@ -386,7 +386,7 @@ print_insn_@arch@ (pc, info) #ifdef CGEN_COMPUTE_ISA isa = CGEN_COMPUTE_ISA (info); #else - isa = 0; + isa = info->insn_sets; #endif /* If we've switched cpu's, close the current table and open a new one. */ -- 2.30.2