From cae1d3e42bbd09f8d7c528528b2e73e23e380752 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 29 Jan 2022 13:48:19 +0000 Subject: [PATCH] re-examining dcache.vhdl, still did not get the store-page address quite right --- src/soc/experiment/dcache.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index eb8b8bf9..b7c059aa 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -1639,8 +1639,8 @@ class DCache(Elaboratable): # See if there is another store waiting # to be done which is in the same real page. with m.If(req.valid): - _ra = req.real_addr[0:SET_SIZE_BITS] - sync += r1.wb.adr[0:SET_SIZE_BITS].eq(_ra) + _ra = req.real_addr[ROW_OFF_BITS:SET_SIZE_BITS] + sync += r1.wb.adr[0:SET_SIZE_BITS-ROW_OFF_BITS].eq(_ra) sync += r1.wb.dat.eq(req.data) sync += r1.wb.sel.eq(req.byte_sel) -- 2.30.2