From cb01740f4730164df65de332663c473cd1d53137 Mon Sep 17 00:00:00 2001 From: Andrey Miroshnikov Date: Wed, 8 Jun 2022 16:43:08 +0100 Subject: [PATCH] Updated the pinmux documentation based on latest dev --- docs/pinmux.mdwn | 131 +++++--- docs/pinmux/gpio-config-word.jpg | Bin 0 -> 8275 bytes docs/pinmux/gpio-mem-layout.jpg | Bin 0 -> 33477 bytes docs/pinmux/iomux-4bank.svg | 311 ++++++++++++++++++ docs/pinmux/n-gpio.svg | 270 +++++++++++++++ docs/pinmux/pinmux-1pin.svg | 542 +++++++++++++++++++++++++++++++ 6 files changed, 1202 insertions(+), 52 deletions(-) create mode 100644 docs/pinmux/gpio-config-word.jpg create mode 100644 docs/pinmux/gpio-mem-layout.jpg create mode 100644 docs/pinmux/iomux-4bank.svg create mode 100644 docs/pinmux/n-gpio.svg create mode 100644 docs/pinmux/pinmux-1pin.svg diff --git a/docs/pinmux.mdwn b/docs/pinmux.mdwn index 7c53f9d15..a3b953c8c 100644 --- a/docs/pinmux.mdwn +++ b/docs/pinmux.mdwn @@ -383,7 +383,7 @@ Signal, but the external peripheral (known as a PHY in Hardware terminology) Firstly: note that the Clock will, obviously, also need to be routed through JTAG Boundary Scan, because, after all, it is being received -through just another ordinary IO Pad, after all. Secondly: note thst +through just another ordinary IO Pad, after all. Secondly: note that if it didn't, then clock skew would occur for that peripheral because although the Data Wires went through JTAG Boundary Scan MUXes, the clock did not. Clearly this would be a problem. @@ -416,72 +416,70 @@ there will be a lag on the output data compared to the incoming (external) clock # Pinmux GPIO Block + The following diagram is an example of a GPIO block with switchable banks and comes from the Ericson presentation on a GPIO architecture. [[!img gpio-block.svg size="800x"]] -The block we are developing is very similar, but is lacking some of configuration of the former (due to complexity and time constraints). +## Our Pinmux Block -## Diagram [[!img banked_gpio_block.jpg size="600x"]] -*(Diagram is missing the "ie" signal as part of the bundle of signals given to the peripherals, will be updated later)* +The block we are developing is very similar, but is lacking some of +configuration of the former (due to complexity and time constraints). -## Explanation -The simple GPIO module is multi-GPIO block integral to the pinmux system. -To make the block flexible, it has a variable number of of I/Os based on an -input parameter. +The implemented pinmux consists of two sub-blocks: -By default, the block is memory-mapped WB bus GPIO. The CPU -core can just write the configuration word to the GPIO row address. From this -perspective, it is no different to a conventional GPIO block. +1. A Wishbone controlled N-GPIO block. -### Bank Select Options -* bank 0 - WB bus has full control (GPIO peripheral) -* bank 1,2,3 - WB bus only controls puen/pden, periphal gets o/oe/i/ie (Not -fully specified how this should be arranged yet) +1. Bank selectable N-port I/O multiplexer (for current usecase set to 4 +ports/banks). -Bank select however, allows to switch over the control of the GPIO block to -another peripheral. The peripheral will be given sole connectivity to the -o/oe/i/ie signals, while additional parameters such as pull up/down will either -be automatically configured (as the case for I2C), or will be configurable -via the WB bus. *(This has not been implemented yet, so open to discussion)* +## The GPIO block + +[[!img n-gpio.svg size="600x"]] + +The GPIO module is multi-GPIO block integral to the pinmux system. +To make the block flexible, it has a variable number of of I/Os based on an +input parameter. + +### Configuration Word -## Configuration Word After a discussion with Luke on IRC (14th January 2022), new layout of the -8-bit data word for configuring the GPIO (through CSR): +8-bit data word for configuring the GPIO (through WB): * oe - Output Enable (see the Ericson presentation for the GPIO diagram) -* ie - Input Enable +* ie - Input Enable *(Not used, as IOPad only supports i/o/oe)* * puen - Pull-Up resistor enable * pden - Pull-Down resistor enable * i/o - When configured as output (oe set), this bit sets/clears output. When configured as input, shows the current state of input (read-only) -* bank_sel[2:0] - Bank Select (only 4 banks used) +* bank[2:0] - Bank Select *(only 4 banks used, bank[2] used for JTAG chain)* ### Simultaneous/Packed Configuration + To make the configuration more efficient, multiple GPIOs can be configured with -one data word. The number of GPIOs in one "row" is dependent on the width of the -WB data bus. +one data word. The number of GPIOs in one "row" is dependent on the WB data bus +*width* and *granuality* (see Wishbone B4 spec, section 3.5 Data Organization +for more details). -If for example, the data bus is 64-bits wide, eight GPIO configuration bytes - -and thus eight GPIOs - are configured in one go. There is no way to specify -which GPIO in a row is configured, so the programmer has to keep the current -state of the configuration as part of the code (essentially a shadow register). +If for example, the data bus is 64-bits wide and granuality is 8, eight GPIO +configuration bytes - and thus eight GPIOs - can be configured in one go. +To configure only certain GPIOs, the WB sel signal can be used (see next +section). -The diagram below shows the layout of the configuration byte, and how it fits -within a 64-bit data word. +The diagram below shows the layout of the configuration byte. -[[!img gpio_csr_example.jpg size="600x"]] +[[!img gpio-config-word.jpg size="600x"]] If the block is created with more GPIOs than can fit in a single data word, the next set of GPIOs can be accessed by incrementing the address. For example, if 16 GPIOs are instantiated and 64-bit data bus is used, GPIOs -0-7 are accessed via address 0, whereas GPIOs 8-15 are accessed by address 8 -(TODO: DOES ADDRESS COUNT WORDS OR BYTES?) +0-7 are accessed via address 0, whereas GPIOs 8-15 are accessed by address 0. + +### Example Memory Map -## Example Memory Map -[[!img gpio_memory_example.jpg size="600x"]] +[[!img gpio-memory-layout.jpg size="600x"]] The diagrams above show the difference in memory layout between 16-GPIO block implemented with 64-bit and 32-bit WB data buses. @@ -531,26 +529,56 @@ then the GPIO number *becomes* the Memory-mapped byte number, hence the use of `len(sel)` above. `len(dat_r)//8` would do as well because these should be equal. -## Combining JTAG BS Chain and Pinmux (In Progress) -[[!img io_mux_bank_planning.JPG size="600x"]] + +## The IO Mux block + +[[!img iomux-4bank.svg size="600x"]] + +This block is an N-to-1 mux and it simultaneously connects: + +* o/oe signals from one of N peripheral ports, to the pad output port + +* i pad port signal to one of N peripheral ports (the rest being set to 0). + +*(NOTE: an N-pin 4-port IOMux has not been implemented yet - do it within the pinmux instead?)* + +## Combined Block + +[[!img pinmux-1pin.svg size="600x"]] + +The GPIO and IOMux blocks are combined in a single block called the +Pinmux block. + +By default, bank 0 is hard-wired to the memory-mapped WB bus GPIO. The CPU +core can just write the configuration word to the GPIO row address. From this +perspective, it is no different to a conventional GPIO block. + +Bank select, allows to switch over the control of the IO pad to +another peripheral. The peripheral will be given sole connectivity to the +o/oe/i signals, while additional parameters such as pull up/down will either +be automatically configured (as the case for I2C), or will be configurable +via the WB bus. *(This has not been implemented yet, so open to discussion)* + +### Bank Select Options + +* bank 0 - WB bus has full control (GPIO peripheral) +* bank 1,2,3 - WB bus only controls puen/pden, periphal gets o/oe/i +(whether ie should be routed out is not finalised yet) + + +### Adding JTAG BS Chain to the Pinmux block (In Progress) The JTAG BS chain need to have access to the bank select bits, to allow selecting different peripherals during testing. At the same time, JTAG may also require access to the WB bus to access GPIO configuration options not available to bank 1/2/3 peripherals. -### Proposal -TODO: REWORK BASED ON GPIO JTAG DIAGRAMS BELOW The proposed JTAG BS chain is as follows: -* Between each peripheral and GPIO block, add a JTAG BS chain. For - example the I2C SDA line will have core o/oe/i/ie, and from JTAG the - pad o/oe/i/ie will connect to the GPIO block's ports 1-3. -* Provide a test port for the GPIO block that gives full access to - configuration (o/oe/i/ie/puen/pden) and bank select. Only allow full - JTAG configuration *IF* ban select bit 2 is set! -* No JTAG chain between WB bus and GPIO port 0 input *(not sure what to - do for this, or whether it is even needed)*. +* Connect puen/pden/bank from GPIO block to the IOMux through JTAG BS chain. +* Connect the i/o/oe pad port from IOMux via JTAG BS chain. +* (?) Test port for configuring GPIO without WB? - utilising bank bit 2? +* (?) Way to drive WB via JTAG? Such a setup would allow the JTAG chain to control the bank select when testing connectivity of the peripherals, as well as give full control to the GPIO @@ -573,9 +601,8 @@ As you can see by the above list, the GPIO block is becoming quite a complex beast. If there are suggestions to simplify or reduce some of the signals, that will be helpful. -The diagrams below show 1-bit GPIO connectivity, as well as the 4-bit case. - -[[!img gpio_jtag_1bit.jpg size="600x"]] +The diagrams above showed 1-bit GPIO connectivity. Below you'll find the +4-bit case *(NOT IMPLEMENTED YET)*. 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port 2 + + i/o/oe + + port 0 + B0 + B1 + B2 + B3 + IO0 + + diff --git a/docs/pinmux/n-gpio.svg b/docs/pinmux/n-gpio.svg new file mode 100644 index 000000000..dad9e50f6 --- /dev/null +++ b/docs/pinmux/n-gpio.svg @@ -0,0 +1,270 @@ + + + + + + + + + + image/svg+xml + + + + + + + + WB + + + + i/o/oe + puen + pden + bank + + + + + + port 0 + + N-GPIO + + i/o/oe + puen + pden + bank + + + + + + port N + + diff --git a/docs/pinmux/pinmux-1pin.svg b/docs/pinmux/pinmux-1pin.svg new file mode 100644 index 000000000..aaa42c093 --- /dev/null +++ b/docs/pinmux/pinmux-1pin.svg @@ -0,0 +1,542 @@ + + + + + + + + + + image/svg+xml + + + + + + + + WB + + + i/o/oe + puen + pden + bank + + + 1-GPIO + + + + i/o/oe + + peripheral 1 + + i/o/oe + + + i/o/oe + + B0 + B1 + B2 + B3 + IO0 + + bank + + JTAG Chain + + + + + + + + + + 1 + 1 + 3 + 3 + + + + + + i/o/oe + puen + pden + + + + I/O Pad + peripheral 2 + peripheral 3 + 4 Bank IOMux + 1-Pin Pinmux + + -- 2.30.2