From cb08f451d01571e0a570e99553624ae7b0d3d075 Mon Sep 17 00:00:00 2001 From: Gert Wollny Date: Mon, 13 Apr 2020 19:51:42 +0200 Subject: [PATCH] gallium/tgsi_to_nir: Set nir_intrinsic_align_mul to 16 and offset to 0 Since the alignment is now checked in the validator we must set it. v2: Use alignement of 4, i.e. dest bit size by eight. v3: Use alignment 16 (Rhys Perry & Jason Ekstand) v4: Use nir_intrinsic_set_align to make it clear that align offset is 0 (Jason) Fixes: e78a7a182524f091e2d77ba97bfbe057c3975cab nir: Assert memory loads are aligned Signed-off-by: Gert Wollny Reviewed-by: Jason Ekstrand Part-of: --- src/gallium/auxiliary/nir/tgsi_to_nir.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c b/src/gallium/auxiliary/nir/tgsi_to_nir.c index 6ac894c85bb..0b96a3e707d 100644 --- a/src/gallium/auxiliary/nir/tgsi_to_nir.c +++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c @@ -736,6 +736,7 @@ ttn_src_for_file_and_index(struct ttn_compile *c, unsigned file, unsigned index, } /* UBO offsets are in bytes, but TGSI gives them to us in vec4's */ offset = nir_ishl(b, offset, nir_imm_int(b, 4)); + nir_intrinsic_set_align(load, 16, 0); } else { nir_intrinsic_set_base(load, index); if (indirect) { -- 2.30.2