From cb1c8c397206ec9e628651b4c9dcaf94db9933af Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 23 Jun 2021 12:01:22 +0100 Subject: [PATCH] whoops svfixedload.mdwn should be in openpower-isa --- openpower/isa/svfixedload.mdwn | 178 --------------------------------- 1 file changed, 178 deletions(-) delete mode 100644 openpower/isa/svfixedload.mdwn diff --git a/openpower/isa/svfixedload.mdwn b/openpower/isa/svfixedload.mdwn deleted file mode 100644 index 72e33d9c6..000000000 --- a/openpower/isa/svfixedload.mdwn +++ /dev/null @@ -1,178 +0,0 @@ - - -# Load Byte and Zero - -SVD-Form - -* lbz RT,D(RA) - -Pseudo-code: - - b <- (RA|0) - EA <- b + EXTS(D) - RT <- [0]*56 || MEM(EA, 1) - -Special Registers Altered: - - None - -# Load Byte and Zero with Update - -D-Form - -* lbzu RT,D(RA) - -Pseudo-code: - - EA <- (RA) + EXTS(D) - RT <- [0] * 56 || MEM(EA, 1) - RA <- EA - -Special Registers Altered: - - None - -# Load Halfword and Zero - -D-Form - -* lhz RT,D(RA) - -Pseudo-code: - - b <- (RA|0) - EA <- b + EXTS(D) - RT <- [0] * 48 || MEM(EA, 2) - -Special Registers Altered: - - None - -# Load Halfword and Zero with Update - -D-Form - -* lhzu RT,D(RA) - -Pseudo-code: - - EA <- (RA) + EXTS(D) - RT <- [0] * 48 || MEM(EA, 2) - RA <- EA - -Special Registers Altered: - - None - -# Load Halfword Algebraic - -D-Form - -* lha RT,D(RA) - -Pseudo-code: - - b <- (RA|0) - EA <- b + EXTS(D) - RT <- EXTS(MEM(EA, 2)) - -Special Registers Altered: - - None - -# Load Halfword Algebraic with Update - -D-Form - -* lhau RT,D(RA) - -Pseudo-code: - - EA <- (RA) + EXTS(D) - RT <- EXTS(MEM(EA, 2)) - RA <- EA - -Special Registers Altered: - - None - -# Load Word and Zero - -D-Form - -* lwz RT,D(RA) - -Pseudo-code: - - b <- (RA|0) - EA <- b + EXTS(D) - RT <- [0] * 32 || MEM(EA, 4) - -Special Registers Altered: - - None - -# Load Word and Zero with Update - -D-Form - -* lwzu RT,D(RA) - -Pseudo-code: - - EA <- (RA) + EXTS(D) - RT <- [0]*32 || MEM(EA, 4) - RA <- EA - -Special Registers Altered: - - None - -# Load Word Algebraic - -DS-Form - -* lwa RT,DS(RA) - -Pseudo-code: - - b <- (RA|0) - EA <- b + EXTS(DS || 0b00) - RT <- EXTS(MEM(EA, 4)) - -Special Registers Altered: - - None - -# Load Doubleword - -DS-Form - -* ld RT,DS(RA) - -Pseudo-code: - - b <- (RA|0) - EA <- b + EXTS(DS || 0b00) - RT <- MEM(EA, 8) - -Special Registers Altered: - - None - -# Load Doubleword with Update Indexed - -DS-Form - -* ldu RT,DS(RA) - -Pseudo-code: - - EA <- (RA) + EXTS(DS || 0b00) - RT <- MEM(EA, 8) - RA <- EA - -Special Registers Altered: - - None - -- 2.30.2