From cb2283389df6fbd2f6aa8393e8d1960123ec72f4 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Sun, 27 Dec 2020 05:00:04 +0000
Subject: [PATCH] CODEOWNERS: add @zachjs as Verilog/AST frontend owner

---
 CODEOWNERS | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/CODEOWNERS b/CODEOWNERS
index 350a62120..0419e6e44 100644
--- a/CODEOWNERS
+++ b/CODEOWNERS
@@ -25,6 +25,9 @@ passes/opt/opt_lut.cc          @whitequark
 # These still override previous lines, so be careful not to
 # accidentally disable any of the above rules.
 
+frontends/verilog/             @zachjs
+frontends/ast/                 @zachjs
+
 techlibs/intel_alm/            @ZirconiumX
 
 # pyosys
-- 
2.30.2