From cb26919c857f002fc17f7c478e7c8f0eb2a7c9b2 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Mon, 16 Mar 2020 15:26:35 +0000 Subject: [PATCH] aarch64: Treat p12-p15 as call-preserved in SVE PCS functions Due to a stupid mistake that I can't really explain, I'd got the treatment of p12-p15 mixed up when adding support for the SVE PCS. The registers are supposed to be call-preserved rather than call-clobbered. The fix is simple, but it has quite a big effect on the PCS tests (as it should!). 2020-03-18 Richard Sandiford gcc/ * config/aarch64/aarch64.c (aarch64_sve_abi): Treat p12-p15 as call-preserved for SVE PCS functions. (aarch64_layout_frame): Cope with up to 12 predicate save slots. Optimize the case in which there are no following vector save slots. gcc/testsuite/ * gcc.target/aarch64/sve/acle/general/cpy_1.c: Leave gaps for in the check-function-bodies patterns for p15 to be saved. * gcc.target/aarch64/sve/pcs/args_1.c (callee_pred): Expect two predicates to be saved. * gcc.target/aarch64/sve/pcs/saves_1_be_nowrap.c (test_1): Expect p12-p15 to be saved and restored. (test_2): Remove p12-p15 from the clobber list. * gcc.target/aarch64/sve/pcs/saves_1_be_wrap.c (test_1): Expect p12-p15 to be saved and restored. (test_2): Remove p12-p15 from the clobber list. * gcc.target/aarch64/sve/pcs/saves_1_le_nowrap.c (test_1): Expect p12-p15 to be saved and restored. (test_2): Remove p12-p15 from the clobber list. * gcc.target/aarch64/sve/pcs/saves_1_le_wrap.c (test_1): Expect p12-p15 to be saved and restored. (test_2): Remove p12-p15 from the clobber list. * gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c: Expect p12-p15 to be saved and restored. * gcc.target/aarch64/sve/pcs/saves_2_be_wrap.c: Likewise. * gcc.target/aarch64/sve/pcs/saves_2_le_nowrap.c: Likewise. * gcc.target/aarch64/sve/pcs/saves_2_le_wrap.c: Likewise. * gcc.target/aarch64/sve/pcs/saves_4_be.c: Likewise. * gcc.target/aarch64/sve/pcs/saves_4_le.c: Likewise. * gcc.target/aarch64/sve/pcs/saves_5_be.c: Likewise. * gcc.target/aarch64/sve/pcs/saves_5_le.c: Likewise. * gcc.target/aarch64/sve/pcs/stack_clash_1.c (test_1): Likewise. (test_2): Remove p12-p15 from the clobber list. * gcc.target/aarch64/sve/pcs/stack_clash_1_128.c (test_1): Expect p12-p15 to be saved and restored. (test_2): Remove p12-p15 from the clobber list. * gcc.target/aarch64/sve/pcs/stack_clash_1_256.c (test_1): Expect p12-p15 to be saved and restored. (test_2): Remove p12-p15 from the clobber list. (test_4): Expect only 16 bytes of stack to be allocated for the predicate save slot. * gcc.target/aarch64/sve/pcs/stack_clash_1_512.c (test_1): Expect p12-p15 to be saved and restored. (test_2): Remove p12-p15 from the clobber list. (test_4): Expect only 16 bytes of stack to be allocated for the predicate save slot. * gcc.target/aarch64/sve/pcs/stack_clash_1_1024.c (test_1): Expect p12-p15 to be saved and restored. (test_2): Remove p12-p15 from the clobber list. (test_4): Expect only 16 bytes of stack to be allocated for the predicate save slot. * gcc.target/aarch64/sve/pcs/stack_clash_1_2048.c (test_1): Expect p12-p15 to be saved and restored. (test_2): Remove p12-p15 from the clobber list. (test_4): Expect only 32 bytes of stack to be allocated for the predicate save slot. * gcc.target/aarch64/sve/pcs/stack_clash_2_256.c: Use z16 rather than p4 to create a vector-sized save slot. * gcc.target/aarch64/sve/pcs/stack_clash_2_512.c: Likewise. * gcc.target/aarch64/sve/pcs/stack_clash_2_1024.c: Likewise. * gcc.target/aarch64/sve/pcs/stack_clash_2_2048.c: Likewise. --- gcc/ChangeLog | 7 + gcc/config/aarch64/aarch64.c | 31 +- gcc/testsuite/ChangeLog | 58 ++++ .../aarch64/sve/acle/general/cpy_1.c | 4 + .../gcc.target/aarch64/sve/pcs/args_1.c | 6 + .../aarch64/sve/pcs/saves_1_be_nowrap.c | 78 +++-- .../aarch64/sve/pcs/saves_1_be_wrap.c | 78 +++-- .../aarch64/sve/pcs/saves_1_le_nowrap.c | 78 +++-- .../aarch64/sve/pcs/saves_1_le_wrap.c | 78 +++-- .../aarch64/sve/pcs/saves_2_be_nowrap.c | 304 ++++++++++-------- .../aarch64/sve/pcs/saves_2_be_wrap.c | 304 ++++++++++-------- .../aarch64/sve/pcs/saves_2_le_nowrap.c | 304 ++++++++++-------- .../aarch64/sve/pcs/saves_2_le_wrap.c | 304 ++++++++++-------- .../gcc.target/aarch64/sve/pcs/saves_4_be.c | 78 +++-- .../gcc.target/aarch64/sve/pcs/saves_4_le.c | 78 +++-- .../gcc.target/aarch64/sve/pcs/saves_5_be.c | 76 +++-- .../gcc.target/aarch64/sve/pcs/saves_5_le.c | 76 +++-- .../aarch64/sve/pcs/stack_clash_1.c | 81 ++--- .../aarch64/sve/pcs/stack_clash_1_1024.c | 82 ++--- .../aarch64/sve/pcs/stack_clash_1_128.c | 78 +++-- .../aarch64/sve/pcs/stack_clash_1_2048.c | 80 ++--- .../aarch64/sve/pcs/stack_clash_1_256.c | 82 ++--- .../aarch64/sve/pcs/stack_clash_1_512.c | 82 ++--- .../aarch64/sve/pcs/stack_clash_2_1024.c | 66 ++-- .../aarch64/sve/pcs/stack_clash_2_2048.c | 66 ++-- .../aarch64/sve/pcs/stack_clash_2_256.c | 66 ++-- .../aarch64/sve/pcs/stack_clash_2_512.c | 66 ++-- 27 files changed, 1511 insertions(+), 1180 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b4d7946a186..1fa291100d0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2020-03-18 Richard Sandiford + + * config/aarch64/aarch64.c (aarch64_sve_abi): Treat p12-p15 as + call-preserved for SVE PCS functions. + (aarch64_layout_frame): Cope with up to 12 predicate save slots. + Optimize the case in which there are no following vector save slots. + 2020-03-18 Richard Biener PR middle-end/94188 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 285341ec07c..26c00969cc1 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -1425,7 +1425,7 @@ aarch64_sve_abi (void) = default_function_abi.full_reg_clobbers (); for (int regno = V8_REGNUM; regno <= V23_REGNUM; ++regno) CLEAR_HARD_REG_BIT (full_reg_clobbers, regno); - for (int regno = P4_REGNUM; regno <= P11_REGNUM; ++regno) + for (int regno = P4_REGNUM; regno <= P15_REGNUM; ++regno) CLEAR_HARD_REG_BIT (full_reg_clobbers, regno); sve_abi.initialize (ARM_PCS_SVE, full_reg_clobbers); } @@ -6008,14 +6008,31 @@ aarch64_layout_frame (void) offset += BYTES_PER_SVE_PRED; } - /* We save a maximum of 8 predicate registers, and since vector - registers are 8 times the size of a predicate register, all the - saved predicates fit within a single vector. Doing this also - rounds the offset to a 128-bit boundary. */ if (maybe_ne (offset, 0)) { - gcc_assert (known_le (offset, vector_save_size)); - offset = vector_save_size; + /* If we have any vector registers to save above the predicate registers, + the offset of the vector register save slots need to be a multiple + of the vector size. This lets us use the immediate forms of LDR/STR + (or LD1/ST1 for big-endian). + + A vector register is 8 times the size of a predicate register, + and we need to save a maximum of 12 predicate registers, so the + first vector register will be at either #1, MUL VL or #2, MUL VL. + + If we don't have any vector registers to save, and we know how + big the predicate save area is, we can just round it up to the + next 16-byte boundary. */ + if (last_fp_reg == (int) INVALID_REGNUM && offset.is_constant ()) + offset = aligned_upper_bound (offset, STACK_BOUNDARY / BITS_PER_UNIT); + else + { + if (known_le (offset, vector_save_size)) + offset = vector_save_size; + else if (known_le (offset, vector_save_size * 2)) + offset = vector_save_size * 2; + else + gcc_unreachable (); + } } /* If we need to save any SVE vector registers, add them next. */ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0b2e4b813f2..3c70254fc6c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,61 @@ +2020-03-18 Richard Sandiford + + * gcc.target/aarch64/sve/acle/general/cpy_1.c: Leave gaps for in the + check-function-bodies patterns for p15 to be saved. + * gcc.target/aarch64/sve/pcs/args_1.c (callee_pred): Expect two + predicates to be saved. + * gcc.target/aarch64/sve/pcs/saves_1_be_nowrap.c (test_1): Expect + p12-p15 to be saved and restored. + (test_2): Remove p12-p15 from the clobber list. + * gcc.target/aarch64/sve/pcs/saves_1_be_wrap.c (test_1): Expect + p12-p15 to be saved and restored. + (test_2): Remove p12-p15 from the clobber list. + * gcc.target/aarch64/sve/pcs/saves_1_le_nowrap.c (test_1): Expect + p12-p15 to be saved and restored. + (test_2): Remove p12-p15 from the clobber list. + * gcc.target/aarch64/sve/pcs/saves_1_le_wrap.c (test_1): Expect + p12-p15 to be saved and restored. + (test_2): Remove p12-p15 from the clobber list. + * gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c: Expect p12-p15 + to be saved and restored. + * gcc.target/aarch64/sve/pcs/saves_2_be_wrap.c: Likewise. + * gcc.target/aarch64/sve/pcs/saves_2_le_nowrap.c: Likewise. + * gcc.target/aarch64/sve/pcs/saves_2_le_wrap.c: Likewise. + * gcc.target/aarch64/sve/pcs/saves_4_be.c: Likewise. + * gcc.target/aarch64/sve/pcs/saves_4_le.c: Likewise. + * gcc.target/aarch64/sve/pcs/saves_5_be.c: Likewise. + * gcc.target/aarch64/sve/pcs/saves_5_le.c: Likewise. + * gcc.target/aarch64/sve/pcs/stack_clash_1.c (test_1): Likewise. + (test_2): Remove p12-p15 from the clobber list. + * gcc.target/aarch64/sve/pcs/stack_clash_1_128.c (test_1): Expect + p12-p15 to be saved and restored. + (test_2): Remove p12-p15 from the clobber list. + * gcc.target/aarch64/sve/pcs/stack_clash_1_256.c (test_1): Expect + p12-p15 to be saved and restored. + (test_2): Remove p12-p15 from the clobber list. + (test_4): Expect only 16 bytes of stack to be allocated for the + predicate save slot. + * gcc.target/aarch64/sve/pcs/stack_clash_1_512.c (test_1): Expect + p12-p15 to be saved and restored. + (test_2): Remove p12-p15 from the clobber list. + (test_4): Expect only 16 bytes of stack to be allocated for the + predicate save slot. + * gcc.target/aarch64/sve/pcs/stack_clash_1_1024.c (test_1): Expect + p12-p15 to be saved and restored. + (test_2): Remove p12-p15 from the clobber list. + (test_4): Expect only 16 bytes of stack to be allocated for the + predicate save slot. + * gcc.target/aarch64/sve/pcs/stack_clash_1_2048.c (test_1): Expect + p12-p15 to be saved and restored. + (test_2): Remove p12-p15 from the clobber list. + (test_4): Expect only 32 bytes of stack to be allocated for the + predicate save slot. + * gcc.target/aarch64/sve/pcs/stack_clash_2_256.c: Use z16 rather + than p4 to create a vector-sized save slot. + * gcc.target/aarch64/sve/pcs/stack_clash_2_512.c: Likewise. + * gcc.target/aarch64/sve/pcs/stack_clash_2_1024.c: Likewise. + * gcc.target/aarch64/sve/pcs/stack_clash_2_2048.c: Likewise. + 2020-03-18 Tobias Burnus * g++.dg/goacc/firstprivate-mappings-1.C: Only set DO_LONG_DOUBLE if diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cpy_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cpy_1.c index 1d8f429caeb..57b56a7e256 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cpy_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cpy_1.c @@ -10,9 +10,11 @@ extern "C" { /* ** dup_x0_m: +** ... ** add (x[0-9]+), x0, #?1 ** mov (p[0-7])\.b, p15\.b ** mov z0\.d, \2/m, \1 +** ... ** ret */ svuint64_t @@ -25,8 +27,10 @@ dup_x0_m (svuint64_t z0, uint64_t x0) /* ** dup_d1_z: +** ... ** mov (p[0-7])\.b, p15\.b ** mov z0\.d, \1/m, d1 +** ... ** ret */ svfloat64_t diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c index fd9932e2e2f..ab7c4a10cfb 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c @@ -6,11 +6,17 @@ /* ** callee_pred: +** addvl sp, sp, #-1 +** str p[0-9]+, \[sp\] +** str p[0-9]+, \[sp, #1, mul vl\] ** ldr (p[0-9]+), \[x0\] ** ldr (p[0-9]+), \[x1\] ** brkpa (p[0-7])\.b, p0/z, p1\.b, p2\.b ** brkpb (p[0-7])\.b, \3/z, p3\.b, \1\.b ** brka p0\.b, \4/z, \2\.b +** ldr p[0-9]+, \[sp\] +** ldr p[0-9]+, \[sp, #1, mul vl\] +** addvl sp, sp, #1 ** ret */ __SVBool_t __attribute__((noipa)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_be_nowrap.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_be_nowrap.c index 4eee0422687..d94e26e11e2 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_be_nowrap.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_be_nowrap.c @@ -6,7 +6,7 @@ /* ** test_1: -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -15,43 +15,47 @@ ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** ptrue p1\.b, all -** st1d z8\.d, p1, \[sp, #1, mul vl\] -** st1d z9\.d, p1, \[sp, #2, mul vl\] -** st1d z10\.d, p1, \[sp, #3, mul vl\] -** st1d z11\.d, p1, \[sp, #4, mul vl\] -** st1d z12\.d, p1, \[sp, #5, mul vl\] -** st1d z13\.d, p1, \[sp, #6, mul vl\] -** st1d z14\.d, p1, \[sp, #7, mul vl\] +** st1d z8\.d, p1, \[sp, #2, mul vl\] +** st1d z9\.d, p1, \[sp, #3, mul vl\] +** st1d z10\.d, p1, \[sp, #4, mul vl\] +** st1d z11\.d, p1, \[sp, #5, mul vl\] +** st1d z12\.d, p1, \[sp, #6, mul vl\] +** st1d z13\.d, p1, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** st1d z15\.d, p1, \[x11, #-8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** st1d z14\.d, p1, \[x11, #-8, mul vl\] +** st1d z15\.d, p1, \[x11, #-7, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** ptrue p0\.b, all ** ptrue p1\.b, all -** ld1d z8\.d, p1/z, \[sp, #1, mul vl\] -** ld1d z9\.d, p1/z, \[sp, #2, mul vl\] -** ld1d z10\.d, p1/z, \[sp, #3, mul vl\] -** ld1d z11\.d, p1/z, \[sp, #4, mul vl\] -** ld1d z12\.d, p1/z, \[sp, #5, mul vl\] -** ld1d z13\.d, p1/z, \[sp, #6, mul vl\] -** ld1d z14\.d, p1/z, \[sp, #7, mul vl\] +** ld1d z8\.d, p1/z, \[sp, #2, mul vl\] +** ld1d z9\.d, p1/z, \[sp, #3, mul vl\] +** ld1d z10\.d, p1/z, \[sp, #4, mul vl\] +** ld1d z11\.d, p1/z, \[sp, #5, mul vl\] +** ld1d z12\.d, p1/z, \[sp, #6, mul vl\] +** ld1d z13\.d, p1/z, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** ld1d z15\.d, p1/z, \[x11, #-8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ld1d z14\.d, p1/z, \[x11, #-8, mul vl\] +** ld1d z15\.d, p1/z, \[x11, #-7, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -60,7 +64,11 @@ ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ret */ svbool_t @@ -87,7 +95,7 @@ test_2 (void) asm volatile ("" ::: "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", - "p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); + "p0", "p1", "p2", "p3"); return svptrue_b8 (); } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_be_wrap.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_be_wrap.c index e88a3dd1da8..a895272e826 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_be_wrap.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_be_wrap.c @@ -6,7 +6,7 @@ /* ** test_1: -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -15,43 +15,47 @@ ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** ptrue p1\.b, all -** st1d z8\.d, p1, \[sp, #1, mul vl\] -** st1d z9\.d, p1, \[sp, #2, mul vl\] -** st1d z10\.d, p1, \[sp, #3, mul vl\] -** st1d z11\.d, p1, \[sp, #4, mul vl\] -** st1d z12\.d, p1, \[sp, #5, mul vl\] -** st1d z13\.d, p1, \[sp, #6, mul vl\] -** st1d z14\.d, p1, \[sp, #7, mul vl\] +** st1d z8\.d, p1, \[sp, #2, mul vl\] +** st1d z9\.d, p1, \[sp, #3, mul vl\] +** st1d z10\.d, p1, \[sp, #4, mul vl\] +** st1d z11\.d, p1, \[sp, #5, mul vl\] +** st1d z12\.d, p1, \[sp, #6, mul vl\] +** st1d z13\.d, p1, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** st1d z15\.d, p1, \[x11, #-8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** st1d z14\.d, p1, \[x11, #-8, mul vl\] +** st1d z15\.d, p1, \[x11, #-7, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** ptrue p0\.b, all ** ptrue p1\.b, all -** ld1d z8\.d, p1/z, \[sp, #1, mul vl\] -** ld1d z9\.d, p1/z, \[sp, #2, mul vl\] -** ld1d z10\.d, p1/z, \[sp, #3, mul vl\] -** ld1d z11\.d, p1/z, \[sp, #4, mul vl\] -** ld1d z12\.d, p1/z, \[sp, #5, mul vl\] -** ld1d z13\.d, p1/z, \[sp, #6, mul vl\] -** ld1d z14\.d, p1/z, \[sp, #7, mul vl\] +** ld1d z8\.d, p1/z, \[sp, #2, mul vl\] +** ld1d z9\.d, p1/z, \[sp, #3, mul vl\] +** ld1d z10\.d, p1/z, \[sp, #4, mul vl\] +** ld1d z11\.d, p1/z, \[sp, #5, mul vl\] +** ld1d z12\.d, p1/z, \[sp, #6, mul vl\] +** ld1d z13\.d, p1/z, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** ld1d z15\.d, p1/z, \[x11, #-8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ld1d z14\.d, p1/z, \[x11, #-8, mul vl\] +** ld1d z15\.d, p1/z, \[x11, #-7, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -60,7 +64,11 @@ ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ret */ svbool_t @@ -87,7 +95,7 @@ test_2 (void) asm volatile ("" ::: "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", - "p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); + "p0", "p1", "p2", "p3"); return svptrue_b8 (); } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_le_nowrap.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_le_nowrap.c index d14cd79b182..72267dc905d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_le_nowrap.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_le_nowrap.c @@ -6,7 +6,7 @@ /* ** test_1: -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -15,39 +15,43 @@ ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** ptrue p0\.b, all -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -56,7 +60,11 @@ ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ret */ svbool_t @@ -83,7 +91,7 @@ test_2 (void) asm volatile ("" ::: "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", - "p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); + "p0", "p1", "p2", "p3"); return svptrue_b8 (); } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_le_wrap.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_le_wrap.c index d81dd8e6bcd..31880784102 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_le_wrap.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_le_wrap.c @@ -6,7 +6,7 @@ /* ** test_1: -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -15,39 +15,43 @@ ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** ptrue p0\.b, all -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -56,7 +60,11 @@ ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ret */ svbool_t @@ -83,7 +91,7 @@ test_2 (void) asm volatile ("" ::: "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", - "p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); + "p0", "p1", "p2", "p3"); return svptrue_b8 (); } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c index 05aa18b3c94..7c4884d0e59 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c @@ -9,7 +9,7 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void); ** calls_standard: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -18,43 +18,47 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void); ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** ptrue p0\.b, all -** st1d z8\.d, p0, \[sp, #1, mul vl\] -** st1d z9\.d, p0, \[sp, #2, mul vl\] -** st1d z10\.d, p0, \[sp, #3, mul vl\] -** st1d z11\.d, p0, \[sp, #4, mul vl\] -** st1d z12\.d, p0, \[sp, #5, mul vl\] -** st1d z13\.d, p0, \[sp, #6, mul vl\] -** st1d z14\.d, p0, \[sp, #7, mul vl\] +** st1d z8\.d, p0, \[sp, #2, mul vl\] +** st1d z9\.d, p0, \[sp, #3, mul vl\] +** st1d z10\.d, p0, \[sp, #4, mul vl\] +** st1d z11\.d, p0, \[sp, #5, mul vl\] +** st1d z12\.d, p0, \[sp, #6, mul vl\] +** st1d z13\.d, p0, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** st1d z15\.d, p0, \[x11, #-8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** st1d z14\.d, p0, \[x11, #-8, mul vl\] +** st1d z15\.d, p0, \[x11, #-7, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** bl standard_callee ** ptrue p0\.b, all -** ld1d z8\.d, p0/z, \[sp, #1, mul vl\] -** ld1d z9\.d, p0/z, \[sp, #2, mul vl\] -** ld1d z10\.d, p0/z, \[sp, #3, mul vl\] -** ld1d z11\.d, p0/z, \[sp, #4, mul vl\] -** ld1d z12\.d, p0/z, \[sp, #5, mul vl\] -** ld1d z13\.d, p0/z, \[sp, #6, mul vl\] -** ld1d z14\.d, p0/z, \[sp, #7, mul vl\] +** ld1d z8\.d, p0/z, \[sp, #2, mul vl\] +** ld1d z9\.d, p0/z, \[sp, #3, mul vl\] +** ld1d z10\.d, p0/z, \[sp, #4, mul vl\] +** ld1d z11\.d, p0/z, \[sp, #5, mul vl\] +** ld1d z12\.d, p0/z, \[sp, #6, mul vl\] +** ld1d z13\.d, p0/z, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** ld1d z15\.d, p0/z, \[x11, #-8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ld1d z14\.d, p0/z, \[x11, #-8, mul vl\] +** ld1d z15\.d, p0/z, \[x11, #-7, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -63,7 +67,11 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void); ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ @@ -73,7 +81,7 @@ void calls_standard (__SVInt8_t x) { standard_callee (); } ** calls_vpcs: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -82,43 +90,47 @@ void calls_standard (__SVInt8_t x) { standard_callee (); } ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** ptrue p0\.b, all -** st1d z8\.d, p0, \[sp, #1, mul vl\] -** st1d z9\.d, p0, \[sp, #2, mul vl\] -** st1d z10\.d, p0, \[sp, #3, mul vl\] -** st1d z11\.d, p0, \[sp, #4, mul vl\] -** st1d z12\.d, p0, \[sp, #5, mul vl\] -** st1d z13\.d, p0, \[sp, #6, mul vl\] -** st1d z14\.d, p0, \[sp, #7, mul vl\] +** st1d z8\.d, p0, \[sp, #2, mul vl\] +** st1d z9\.d, p0, \[sp, #3, mul vl\] +** st1d z10\.d, p0, \[sp, #4, mul vl\] +** st1d z11\.d, p0, \[sp, #5, mul vl\] +** st1d z12\.d, p0, \[sp, #6, mul vl\] +** st1d z13\.d, p0, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** st1d z15\.d, p0, \[x11, #-8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** st1d z14\.d, p0, \[x11, #-8, mul vl\] +** st1d z15\.d, p0, \[x11, #-7, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** bl vpcs_callee ** ptrue p0\.b, all -** ld1d z8\.d, p0/z, \[sp, #1, mul vl\] -** ld1d z9\.d, p0/z, \[sp, #2, mul vl\] -** ld1d z10\.d, p0/z, \[sp, #3, mul vl\] -** ld1d z11\.d, p0/z, \[sp, #4, mul vl\] -** ld1d z12\.d, p0/z, \[sp, #5, mul vl\] -** ld1d z13\.d, p0/z, \[sp, #6, mul vl\] -** ld1d z14\.d, p0/z, \[sp, #7, mul vl\] +** ld1d z8\.d, p0/z, \[sp, #2, mul vl\] +** ld1d z9\.d, p0/z, \[sp, #3, mul vl\] +** ld1d z10\.d, p0/z, \[sp, #4, mul vl\] +** ld1d z11\.d, p0/z, \[sp, #5, mul vl\] +** ld1d z12\.d, p0/z, \[sp, #6, mul vl\] +** ld1d z13\.d, p0/z, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** ld1d z15\.d, p0/z, \[x11, #-8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ld1d z14\.d, p0/z, \[x11, #-8, mul vl\] +** ld1d z15\.d, p0/z, \[x11, #-7, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -127,7 +139,11 @@ void calls_standard (__SVInt8_t x) { standard_callee (); } ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ @@ -137,7 +153,7 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); } ** calls_standard_ptr: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -146,43 +162,47 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); } ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** ptrue p0\.b, all -** st1d z8\.d, p0, \[sp, #1, mul vl\] -** st1d z9\.d, p0, \[sp, #2, mul vl\] -** st1d z10\.d, p0, \[sp, #3, mul vl\] -** st1d z11\.d, p0, \[sp, #4, mul vl\] -** st1d z12\.d, p0, \[sp, #5, mul vl\] -** st1d z13\.d, p0, \[sp, #6, mul vl\] -** st1d z14\.d, p0, \[sp, #7, mul vl\] +** st1d z8\.d, p0, \[sp, #2, mul vl\] +** st1d z9\.d, p0, \[sp, #3, mul vl\] +** st1d z10\.d, p0, \[sp, #4, mul vl\] +** st1d z11\.d, p0, \[sp, #5, mul vl\] +** st1d z12\.d, p0, \[sp, #6, mul vl\] +** st1d z13\.d, p0, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** st1d z15\.d, p0, \[x11, #-8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** st1d z14\.d, p0, \[x11, #-8, mul vl\] +** st1d z15\.d, p0, \[x11, #-7, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** blr x0 ** ptrue p0\.b, all -** ld1d z8\.d, p0/z, \[sp, #1, mul vl\] -** ld1d z9\.d, p0/z, \[sp, #2, mul vl\] -** ld1d z10\.d, p0/z, \[sp, #3, mul vl\] -** ld1d z11\.d, p0/z, \[sp, #4, mul vl\] -** ld1d z12\.d, p0/z, \[sp, #5, mul vl\] -** ld1d z13\.d, p0/z, \[sp, #6, mul vl\] -** ld1d z14\.d, p0/z, \[sp, #7, mul vl\] +** ld1d z8\.d, p0/z, \[sp, #2, mul vl\] +** ld1d z9\.d, p0/z, \[sp, #3, mul vl\] +** ld1d z10\.d, p0/z, \[sp, #4, mul vl\] +** ld1d z11\.d, p0/z, \[sp, #5, mul vl\] +** ld1d z12\.d, p0/z, \[sp, #6, mul vl\] +** ld1d z13\.d, p0/z, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** ld1d z15\.d, p0/z, \[x11, #-8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ld1d z14\.d, p0/z, \[x11, #-8, mul vl\] +** ld1d z15\.d, p0/z, \[x11, #-7, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -191,7 +211,11 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); } ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ @@ -205,7 +229,7 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void)) ** calls_vpcs_ptr: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -214,43 +238,47 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void)) ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** ptrue p0\.b, all -** st1d z8\.d, p0, \[sp, #1, mul vl\] -** st1d z9\.d, p0, \[sp, #2, mul vl\] -** st1d z10\.d, p0, \[sp, #3, mul vl\] -** st1d z11\.d, p0, \[sp, #4, mul vl\] -** st1d z12\.d, p0, \[sp, #5, mul vl\] -** st1d z13\.d, p0, \[sp, #6, mul vl\] -** st1d z14\.d, p0, \[sp, #7, mul vl\] +** st1d z8\.d, p0, \[sp, #2, mul vl\] +** st1d z9\.d, p0, \[sp, #3, mul vl\] +** st1d z10\.d, p0, \[sp, #4, mul vl\] +** st1d z11\.d, p0, \[sp, #5, mul vl\] +** st1d z12\.d, p0, \[sp, #6, mul vl\] +** st1d z13\.d, p0, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** st1d z15\.d, p0, \[x11, #-8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** st1d z14\.d, p0, \[x11, #-8, mul vl\] +** st1d z15\.d, p0, \[x11, #-7, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** blr x0 ** ptrue p0\.b, all -** ld1d z8\.d, p0/z, \[sp, #1, mul vl\] -** ld1d z9\.d, p0/z, \[sp, #2, mul vl\] -** ld1d z10\.d, p0/z, \[sp, #3, mul vl\] -** ld1d z11\.d, p0/z, \[sp, #4, mul vl\] -** ld1d z12\.d, p0/z, \[sp, #5, mul vl\] -** ld1d z13\.d, p0/z, \[sp, #6, mul vl\] -** ld1d z14\.d, p0/z, \[sp, #7, mul vl\] +** ld1d z8\.d, p0/z, \[sp, #2, mul vl\] +** ld1d z9\.d, p0/z, \[sp, #3, mul vl\] +** ld1d z10\.d, p0/z, \[sp, #4, mul vl\] +** ld1d z11\.d, p0/z, \[sp, #5, mul vl\] +** ld1d z12\.d, p0/z, \[sp, #6, mul vl\] +** ld1d z13\.d, p0/z, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** ld1d z15\.d, p0/z, \[x11, #-8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ld1d z14\.d, p0/z, \[x11, #-8, mul vl\] +** ld1d z15\.d, p0/z, \[x11, #-7, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -259,7 +287,11 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void)) ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_be_wrap.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_be_wrap.c index 85b7794d760..872364f8752 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_be_wrap.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_be_wrap.c @@ -9,7 +9,7 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void); ** calls_standard: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -18,43 +18,47 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void); ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** ptrue p0\.b, all -** st1d z8\.d, p0, \[sp, #1, mul vl\] -** st1d z9\.d, p0, \[sp, #2, mul vl\] -** st1d z10\.d, p0, \[sp, #3, mul vl\] -** st1d z11\.d, p0, \[sp, #4, mul vl\] -** st1d z12\.d, p0, \[sp, #5, mul vl\] -** st1d z13\.d, p0, \[sp, #6, mul vl\] -** st1d z14\.d, p0, \[sp, #7, mul vl\] +** st1d z8\.d, p0, \[sp, #2, mul vl\] +** st1d z9\.d, p0, \[sp, #3, mul vl\] +** st1d z10\.d, p0, \[sp, #4, mul vl\] +** st1d z11\.d, p0, \[sp, #5, mul vl\] +** st1d z12\.d, p0, \[sp, #6, mul vl\] +** st1d z13\.d, p0, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** st1d z15\.d, p0, \[x11, #-8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** st1d z14\.d, p0, \[x11, #-8, mul vl\] +** st1d z15\.d, p0, \[x11, #-7, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** bl standard_callee ** ptrue p0\.b, all -** ld1d z8\.d, p0/z, \[sp, #1, mul vl\] -** ld1d z9\.d, p0/z, \[sp, #2, mul vl\] -** ld1d z10\.d, p0/z, \[sp, #3, mul vl\] -** ld1d z11\.d, p0/z, \[sp, #4, mul vl\] -** ld1d z12\.d, p0/z, \[sp, #5, mul vl\] -** ld1d z13\.d, p0/z, \[sp, #6, mul vl\] -** ld1d z14\.d, p0/z, \[sp, #7, mul vl\] +** ld1d z8\.d, p0/z, \[sp, #2, mul vl\] +** ld1d z9\.d, p0/z, \[sp, #3, mul vl\] +** ld1d z10\.d, p0/z, \[sp, #4, mul vl\] +** ld1d z11\.d, p0/z, \[sp, #5, mul vl\] +** ld1d z12\.d, p0/z, \[sp, #6, mul vl\] +** ld1d z13\.d, p0/z, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** ld1d z15\.d, p0/z, \[x11, #-8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ld1d z14\.d, p0/z, \[x11, #-8, mul vl\] +** ld1d z15\.d, p0/z, \[x11, #-7, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -63,7 +67,11 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void); ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ @@ -73,7 +81,7 @@ void calls_standard (__SVInt8_t x) { standard_callee (); } ** calls_vpcs: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -82,43 +90,47 @@ void calls_standard (__SVInt8_t x) { standard_callee (); } ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** ptrue p0\.b, all -** st1d z8\.d, p0, \[sp, #1, mul vl\] -** st1d z9\.d, p0, \[sp, #2, mul vl\] -** st1d z10\.d, p0, \[sp, #3, mul vl\] -** st1d z11\.d, p0, \[sp, #4, mul vl\] -** st1d z12\.d, p0, \[sp, #5, mul vl\] -** st1d z13\.d, p0, \[sp, #6, mul vl\] -** st1d z14\.d, p0, \[sp, #7, mul vl\] +** st1d z8\.d, p0, \[sp, #2, mul vl\] +** st1d z9\.d, p0, \[sp, #3, mul vl\] +** st1d z10\.d, p0, \[sp, #4, mul vl\] +** st1d z11\.d, p0, \[sp, #5, mul vl\] +** st1d z12\.d, p0, \[sp, #6, mul vl\] +** st1d z13\.d, p0, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** st1d z15\.d, p0, \[x11, #-8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** st1d z14\.d, p0, \[x11, #-8, mul vl\] +** st1d z15\.d, p0, \[x11, #-7, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** bl vpcs_callee ** ptrue p0\.b, all -** ld1d z8\.d, p0/z, \[sp, #1, mul vl\] -** ld1d z9\.d, p0/z, \[sp, #2, mul vl\] -** ld1d z10\.d, p0/z, \[sp, #3, mul vl\] -** ld1d z11\.d, p0/z, \[sp, #4, mul vl\] -** ld1d z12\.d, p0/z, \[sp, #5, mul vl\] -** ld1d z13\.d, p0/z, \[sp, #6, mul vl\] -** ld1d z14\.d, p0/z, \[sp, #7, mul vl\] +** ld1d z8\.d, p0/z, \[sp, #2, mul vl\] +** ld1d z9\.d, p0/z, \[sp, #3, mul vl\] +** ld1d z10\.d, p0/z, \[sp, #4, mul vl\] +** ld1d z11\.d, p0/z, \[sp, #5, mul vl\] +** ld1d z12\.d, p0/z, \[sp, #6, mul vl\] +** ld1d z13\.d, p0/z, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** ld1d z15\.d, p0/z, \[x11, #-8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ld1d z14\.d, p0/z, \[x11, #-8, mul vl\] +** ld1d z15\.d, p0/z, \[x11, #-7, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -127,7 +139,11 @@ void calls_standard (__SVInt8_t x) { standard_callee (); } ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ @@ -137,7 +153,7 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); } ** calls_standard_ptr: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -146,43 +162,47 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); } ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** ptrue p0\.b, all -** st1d z8\.d, p0, \[sp, #1, mul vl\] -** st1d z9\.d, p0, \[sp, #2, mul vl\] -** st1d z10\.d, p0, \[sp, #3, mul vl\] -** st1d z11\.d, p0, \[sp, #4, mul vl\] -** st1d z12\.d, p0, \[sp, #5, mul vl\] -** st1d z13\.d, p0, \[sp, #6, mul vl\] -** st1d z14\.d, p0, \[sp, #7, mul vl\] +** st1d z8\.d, p0, \[sp, #2, mul vl\] +** st1d z9\.d, p0, \[sp, #3, mul vl\] +** st1d z10\.d, p0, \[sp, #4, mul vl\] +** st1d z11\.d, p0, \[sp, #5, mul vl\] +** st1d z12\.d, p0, \[sp, #6, mul vl\] +** st1d z13\.d, p0, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** st1d z15\.d, p0, \[x11, #-8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** st1d z14\.d, p0, \[x11, #-8, mul vl\] +** st1d z15\.d, p0, \[x11, #-7, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** blr x0 ** ptrue p0\.b, all -** ld1d z8\.d, p0/z, \[sp, #1, mul vl\] -** ld1d z9\.d, p0/z, \[sp, #2, mul vl\] -** ld1d z10\.d, p0/z, \[sp, #3, mul vl\] -** ld1d z11\.d, p0/z, \[sp, #4, mul vl\] -** ld1d z12\.d, p0/z, \[sp, #5, mul vl\] -** ld1d z13\.d, p0/z, \[sp, #6, mul vl\] -** ld1d z14\.d, p0/z, \[sp, #7, mul vl\] +** ld1d z8\.d, p0/z, \[sp, #2, mul vl\] +** ld1d z9\.d, p0/z, \[sp, #3, mul vl\] +** ld1d z10\.d, p0/z, \[sp, #4, mul vl\] +** ld1d z11\.d, p0/z, \[sp, #5, mul vl\] +** ld1d z12\.d, p0/z, \[sp, #6, mul vl\] +** ld1d z13\.d, p0/z, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** ld1d z15\.d, p0/z, \[x11, #-8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ld1d z14\.d, p0/z, \[x11, #-8, mul vl\] +** ld1d z15\.d, p0/z, \[x11, #-7, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -191,7 +211,11 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); } ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ @@ -205,7 +229,7 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void)) ** calls_vpcs_ptr: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -214,43 +238,47 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void)) ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** ptrue p0\.b, all -** st1d z8\.d, p0, \[sp, #1, mul vl\] -** st1d z9\.d, p0, \[sp, #2, mul vl\] -** st1d z10\.d, p0, \[sp, #3, mul vl\] -** st1d z11\.d, p0, \[sp, #4, mul vl\] -** st1d z12\.d, p0, \[sp, #5, mul vl\] -** st1d z13\.d, p0, \[sp, #6, mul vl\] -** st1d z14\.d, p0, \[sp, #7, mul vl\] +** st1d z8\.d, p0, \[sp, #2, mul vl\] +** st1d z9\.d, p0, \[sp, #3, mul vl\] +** st1d z10\.d, p0, \[sp, #4, mul vl\] +** st1d z11\.d, p0, \[sp, #5, mul vl\] +** st1d z12\.d, p0, \[sp, #6, mul vl\] +** st1d z13\.d, p0, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** st1d z15\.d, p0, \[x11, #-8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** st1d z14\.d, p0, \[x11, #-8, mul vl\] +** st1d z15\.d, p0, \[x11, #-7, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** blr x0 ** ptrue p0\.b, all -** ld1d z8\.d, p0/z, \[sp, #1, mul vl\] -** ld1d z9\.d, p0/z, \[sp, #2, mul vl\] -** ld1d z10\.d, p0/z, \[sp, #3, mul vl\] -** ld1d z11\.d, p0/z, \[sp, #4, mul vl\] -** ld1d z12\.d, p0/z, \[sp, #5, mul vl\] -** ld1d z13\.d, p0/z, \[sp, #6, mul vl\] -** ld1d z14\.d, p0/z, \[sp, #7, mul vl\] +** ld1d z8\.d, p0/z, \[sp, #2, mul vl\] +** ld1d z9\.d, p0/z, \[sp, #3, mul vl\] +** ld1d z10\.d, p0/z, \[sp, #4, mul vl\] +** ld1d z11\.d, p0/z, \[sp, #5, mul vl\] +** ld1d z12\.d, p0/z, \[sp, #6, mul vl\] +** ld1d z13\.d, p0/z, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** ld1d z15\.d, p0/z, \[x11, #-8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ld1d z14\.d, p0/z, \[x11, #-8, mul vl\] +** ld1d z15\.d, p0/z, \[x11, #-7, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -259,7 +287,11 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void)) ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_le_nowrap.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_le_nowrap.c index 0fcd357a069..4ba71c0abae 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_le_nowrap.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_le_nowrap.c @@ -9,7 +9,7 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void); ** calls_standard: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -18,39 +18,43 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void); ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** bl standard_callee -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -59,7 +63,11 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void); ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ @@ -69,7 +77,7 @@ void calls_standard (__SVInt8_t x) { standard_callee (); } ** calls_vpcs: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -78,39 +86,43 @@ void calls_standard (__SVInt8_t x) { standard_callee (); } ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** bl vpcs_callee -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -119,7 +131,11 @@ void calls_standard (__SVInt8_t x) { standard_callee (); } ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ @@ -129,7 +145,7 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); } ** calls_standard_ptr: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -138,39 +154,43 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); } ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** blr x0 -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -179,7 +199,11 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); } ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ @@ -193,7 +217,7 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void)) ** calls_vpcs_ptr: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -202,39 +226,43 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void)) ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** blr x0 -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -243,7 +271,11 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void)) ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_le_wrap.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_le_wrap.c index e81194c748b..c3acd40faca 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_le_wrap.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_le_wrap.c @@ -9,7 +9,7 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void); ** calls_standard: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -18,39 +18,43 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void); ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** bl standard_callee -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -59,7 +63,11 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void); ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ @@ -69,7 +77,7 @@ void calls_standard (__SVInt8_t x) { standard_callee (); } ** calls_vpcs: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -78,39 +86,43 @@ void calls_standard (__SVInt8_t x) { standard_callee (); } ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** bl vpcs_callee -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -119,7 +131,11 @@ void calls_standard (__SVInt8_t x) { standard_callee (); } ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ @@ -129,7 +145,7 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); } ** calls_standard_ptr: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -138,39 +154,43 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); } ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** blr x0 -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -179,7 +199,11 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); } ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ @@ -193,7 +217,7 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void)) ** calls_vpcs_ptr: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -202,39 +226,43 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void)) ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** blr x0 -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -243,7 +271,11 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void)) ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_4_be.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_4_be.c index c42699dc728..aa67bee255d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_4_be.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_4_be.c @@ -14,7 +14,7 @@ void standard_callee (__SVInt8_t *); ** stp x29, x30, \[sp\] ** ) ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -23,45 +23,49 @@ void standard_callee (__SVInt8_t *); ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** ptrue p0\.b, all -** st1d z8\.d, p0, \[sp, #1, mul vl\] -** st1d z9\.d, p0, \[sp, #2, mul vl\] -** st1d z10\.d, p0, \[sp, #3, mul vl\] -** st1d z11\.d, p0, \[sp, #4, mul vl\] -** st1d z12\.d, p0, \[sp, #5, mul vl\] -** st1d z13\.d, p0, \[sp, #6, mul vl\] -** st1d z14\.d, p0, \[sp, #7, mul vl\] +** st1d z8\.d, p0, \[sp, #2, mul vl\] +** st1d z9\.d, p0, \[sp, #3, mul vl\] +** st1d z10\.d, p0, \[sp, #4, mul vl\] +** st1d z11\.d, p0, \[sp, #5, mul vl\] +** st1d z12\.d, p0, \[sp, #6, mul vl\] +** st1d z13\.d, p0, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** st1d z15\.d, p0, \[x11, #-8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] -** addvl x0, sp, #17 +** st1d z14\.d, p0, \[x11, #-8, mul vl\] +** st1d z15\.d, p0, \[x11, #-7, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] +** addvl x0, sp, #18 ** add x0, x0, #?16 ** bl standard_callee ** ptrue p0\.b, all -** ld1d z8\.d, p0/z, \[sp, #1, mul vl\] -** ld1d z9\.d, p0/z, \[sp, #2, mul vl\] -** ld1d z10\.d, p0/z, \[sp, #3, mul vl\] -** ld1d z11\.d, p0/z, \[sp, #4, mul vl\] -** ld1d z12\.d, p0/z, \[sp, #5, mul vl\] -** ld1d z13\.d, p0/z, \[sp, #6, mul vl\] -** ld1d z14\.d, p0/z, \[sp, #7, mul vl\] +** ld1d z8\.d, p0/z, \[sp, #2, mul vl\] +** ld1d z9\.d, p0/z, \[sp, #3, mul vl\] +** ld1d z10\.d, p0/z, \[sp, #4, mul vl\] +** ld1d z11\.d, p0/z, \[sp, #5, mul vl\] +** ld1d z12\.d, p0/z, \[sp, #6, mul vl\] +** ld1d z13\.d, p0/z, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** ld1d z15\.d, p0/z, \[x11, #-8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ld1d z14\.d, p0/z, \[x11, #-8, mul vl\] +** ld1d z15\.d, p0/z, \[x11, #-7, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -70,7 +74,11 @@ void standard_callee (__SVInt8_t *); ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ( ** ldp x29, x30, \[sp\], 16 ** addvl sp, sp, #1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_4_le.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_4_le.c index 49fe96800b9..ab232d7ee7a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_4_le.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_4_le.c @@ -14,7 +14,7 @@ void standard_callee (__SVInt8_t *); ** stp x29, x30, \[sp\] ** ) ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -23,41 +23,45 @@ void standard_callee (__SVInt8_t *); ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] -** addvl x0, sp, #17 +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] +** addvl x0, sp, #18 ** add x0, x0, #?16 ** bl standard_callee -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -66,7 +70,11 @@ void standard_callee (__SVInt8_t *); ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ( ** ldp x29, x30, \[sp\], 16 ** addvl sp, sp, #1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_5_be.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_5_be.c index dc3282eee61..cce9cd82df3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_5_be.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_5_be.c @@ -8,40 +8,40 @@ void standard_callee (void); ** calls_standard: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** ptrue p0\.b, all -** st1d z8\.d, p0, \[sp, #1, mul vl\] -** st1d z9\.d, p0, \[sp, #2, mul vl\] -** st1d z10\.d, p0, \[sp, #3, mul vl\] -** st1d z11\.d, p0, \[sp, #4, mul vl\] -** st1d z12\.d, p0, \[sp, #5, mul vl\] -** st1d z13\.d, p0, \[sp, #6, mul vl\] -** st1d z14\.d, p0, \[sp, #7, mul vl\] +** st1d z8\.d, p0, \[sp, #2, mul vl\] +** st1d z9\.d, p0, \[sp, #3, mul vl\] +** st1d z10\.d, p0, \[sp, #4, mul vl\] +** st1d z11\.d, p0, \[sp, #5, mul vl\] +** st1d z12\.d, p0, \[sp, #6, mul vl\] +** st1d z13\.d, p0, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** st1d z15\.d, p0, \[x11, #-8, mul vl\] +** st1d z14\.d, p0, \[x11, #-8, mul vl\] +** st1d z15\.d, p0, \[x11, #-7, mul vl\] ** cbnz w0, \.L[0-9]+ ** ptrue p0\.b, all -** ld1d z8\.d, p0/z, \[sp, #1, mul vl\] -** ld1d z9\.d, p0/z, \[sp, #2, mul vl\] -** ld1d z10\.d, p0/z, \[sp, #3, mul vl\] -** ld1d z11\.d, p0/z, \[sp, #4, mul vl\] -** ld1d z12\.d, p0/z, \[sp, #5, mul vl\] -** ld1d z13\.d, p0/z, \[sp, #6, mul vl\] -** ld1d z14\.d, p0/z, \[sp, #7, mul vl\] +** ld1d z8\.d, p0/z, \[sp, #2, mul vl\] +** ld1d z9\.d, p0/z, \[sp, #3, mul vl\] +** ld1d z10\.d, p0/z, \[sp, #4, mul vl\] +** ld1d z11\.d, p0/z, \[sp, #5, mul vl\] +** ld1d z12\.d, p0/z, \[sp, #6, mul vl\] +** ld1d z13\.d, p0/z, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** ld1d z15\.d, p0/z, \[x11, #-8, mul vl\] -** addvl sp, sp, #17 +** ld1d z14\.d, p0/z, \[x11, #-8, mul vl\] +** ld1d z15\.d, p0/z, \[x11, #-7, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret ** ... -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -50,15 +50,19 @@ void standard_callee (void); ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** bl standard_callee -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -67,6 +71,10 @@ void standard_callee (void); ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] ** b \.L[0-9]+ */ void diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_5_le.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_5_le.c index 0d29ff2fd47..0c4fff8da84 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_5_le.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_5_le.c @@ -8,29 +8,29 @@ void standard_callee (void); ** calls_standard: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 -** str z8, \[sp, #1, mul vl\] +** addvl sp, sp, #-18 +** str z8, \[sp, #2, mul vl\] ** cbnz w0, \.L[0-9]+ -** ldr z8, \[sp, #1, mul vl\] -** addvl sp, sp, #17 +** ldr z8, \[sp, #2, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret ** ... -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -39,22 +39,26 @@ void standard_callee (void); ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** bl standard_callee -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -63,6 +67,10 @@ void standard_callee (void); ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] ** b \.L[0-9]+ */ void diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1.c index 485d01875cd..110947a6c4a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1.c @@ -6,9 +6,8 @@ /* ** test_1: -** cntb x12 -** mov x13, #?17 -** mul x12, x12, x13 +** cntd x12, all, mul #9 +** lsl x12, x12, #?4 ** mov x11, sp ** ... ** sub sp, sp, x12 @@ -20,39 +19,43 @@ ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** ptrue p0\.b, all -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -61,7 +64,11 @@ ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ret */ svbool_t @@ -88,7 +95,7 @@ test_2 (void) asm volatile ("" ::: "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", - "p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); + "p0", "p1", "p2", "p3"); return svptrue_b8 (); } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_1024.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_1024.c index 087e8db9e83..6590e4a8c46 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_1024.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_1024.c @@ -6,7 +6,7 @@ /* ** test_1: -** sub sp, sp, #2176 +** sub sp, sp, #2304 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -15,39 +15,43 @@ ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** ptrue p0\.b, vl128 -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -56,7 +60,11 @@ ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** add sp, sp, #?2176 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** add sp, sp, #?2304 ** ret */ svbool_t @@ -83,7 +91,7 @@ test_2 (void) asm volatile ("" ::: "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", - "p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); + "p0", "p1", "p2", "p3"); return svptrue_b8 (); } @@ -121,11 +129,11 @@ test_3 (void) /* ** test_4: -** sub sp, sp, #128 +** sub sp, sp, #16 ** str p4, \[sp\] ** ptrue p0\.b, vl128 ** ldr p4, \[sp\] -** add sp, sp, #?128 +** add sp, sp, #?16 ** ret */ svbool_t diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_128.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_128.c index 0eb7d10f7a0..404301dc0c1 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_128.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_128.c @@ -6,7 +6,7 @@ /* ** test_1: -** sub sp, sp, #272 +** sub sp, sp, #288 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -15,39 +15,43 @@ ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** ptrue p0\.b, vl16 -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -56,7 +60,11 @@ ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** add sp, sp, #?272 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** add sp, sp, #?288 ** ret */ svbool_t @@ -83,7 +91,7 @@ test_2 (void) asm volatile ("" ::: "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", - "p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); + "p0", "p1", "p2", "p3"); return svptrue_b8 (); } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_2048.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_2048.c index e8dc5d5e4c4..113ccc131d6 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_2048.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_2048.c @@ -6,7 +6,7 @@ /* ** test_1: -** mov x12, #?4352 +** mov x12, #?4608 ** sub sp, sp, x12 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] @@ -16,39 +16,43 @@ ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** ptrue p0\.b, vl256 -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -57,6 +61,10 @@ ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] ** add sp, sp, x12 ** ret */ @@ -84,7 +92,7 @@ test_2 (void) asm volatile ("" ::: "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", - "p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); + "p0", "p1", "p2", "p3"); return svptrue_b8 (); } @@ -122,11 +130,11 @@ test_3 (void) /* ** test_4: -** sub sp, sp, #256 +** sub sp, sp, #32 ** str p4, \[sp\] ** ptrue p0\.b, vl256 ** ldr p4, \[sp\] -** add sp, sp, #?256 +** add sp, sp, #?32 ** ret */ svbool_t diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_256.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_256.c index 73c49e4d4f7..0f71cecdc80 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_256.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_256.c @@ -6,7 +6,7 @@ /* ** test_1: -** sub sp, sp, #544 +** sub sp, sp, #576 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -15,39 +15,43 @@ ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** ptrue p0\.b, vl32 -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -56,7 +60,11 @@ ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** add sp, sp, #?544 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** add sp, sp, #?576 ** ret */ svbool_t @@ -83,7 +91,7 @@ test_2 (void) asm volatile ("" ::: "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", - "p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); + "p0", "p1", "p2", "p3"); return svptrue_b8 (); } @@ -121,11 +129,11 @@ test_3 (void) /* ** test_4: -** sub sp, sp, #32 +** sub sp, sp, #16 ** str p4, \[sp\] ** ptrue p0\.b, vl32 ** ldr p4, \[sp\] -** add sp, sp, #?32 +** add sp, sp, #?16 ** ret */ svbool_t diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_512.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_512.c index d4b524147a0..8edbd0459b2 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_512.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_512.c @@ -6,7 +6,7 @@ /* ** test_1: -** sub sp, sp, #1088 +** sub sp, sp, #1152 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -15,39 +15,43 @@ ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** ptrue p0\.b, vl64 -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -56,7 +60,11 @@ ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** add sp, sp, #?1088 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** add sp, sp, #?1152 ** ret */ svbool_t @@ -83,7 +91,7 @@ test_2 (void) asm volatile ("" ::: "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", - "p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); + "p0", "p1", "p2", "p3"); return svptrue_b8 (); } @@ -121,11 +129,11 @@ test_3 (void) /* ** test_4: -** sub sp, sp, #64 +** sub sp, sp, #16 ** str p4, \[sp\] ** ptrue p0\.b, vl64 ** ldr p4, \[sp\] -** add sp, sp, #?64 +** add sp, sp, #?16 ** ret */ svbool_t diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_1024.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_1024.c index d5a9d4444b3..e31200fc22f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_1024.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_1024.c @@ -10,10 +10,10 @@ svbool_t take_stack_args (volatile void *, void *, int, int, int, /* ** test_1: ** sub sp, sp, #144 -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl128 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?144 ** ret */ @@ -21,7 +21,7 @@ svbool_t test_1 (void) { volatile int x = 1; - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -30,10 +30,10 @@ test_1 (void) ** sub sp, sp, #176 ** stp x24, x25, \[sp, 128\] ** str x26, \[sp, 144\] -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl128 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** ldp x24, x25, \[sp, 128\] ** ldr x26, \[sp, 144\] ** add sp, sp, #?176 @@ -43,7 +43,7 @@ svbool_t test_2 (void) { volatile int x = 1; - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } @@ -53,10 +53,10 @@ test_2 (void) ** sub sp, sp, x12 ** stp x24, x25, \[sp, 128\] ** str x26, \[sp, 144\] -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl128 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** ldp x24, x25, \[sp, 128\] ** ldr x26, \[sp, 144\] ** add sp, sp, x12 @@ -66,17 +66,17 @@ svbool_t test_3 (void) { volatile int x[1024]; - asm volatile ("" :: "r" (x) : "p4", "x24", "x25", "x26"); + asm volatile ("" :: "r" (x) : "z16", "x24", "x25", "x26"); return svptrue_b8 (); } /* ** test_4: ** sub sp, sp, #256 -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.h, vl64 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?256 ** ret */ @@ -85,7 +85,7 @@ test_4 (void) { volatile svint32_t b; b = svdup_s32 (1); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b16 (); } @@ -94,10 +94,10 @@ test_4 (void) ** sub sp, sp, #288 ** stp x24, x25, \[sp, 128\] ** str x26, \[sp, 144\] -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.h, vl64 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** ldp x24, x25, \[sp, 128\] ** ldr x26, \[sp, 144\] ** add sp, sp, #?288 @@ -108,7 +108,7 @@ test_5 (void) { volatile svint32_t b; b = svdup_s32 (1); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b16 (); } @@ -117,11 +117,11 @@ test_5 (void) ** stp x29, x30, \[sp, -16\]! ** mov x29, sp ** sub sp, sp, #128 -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl128 ** add sp, sp, #?16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?128 ** ldp x29, x30, \[sp\], 16 ** ret @@ -130,7 +130,7 @@ svbool_t test_6 (void) { take_stack_args (0, 0, 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -140,12 +140,12 @@ test_6 (void) ** sub sp, sp, x12 ** stp x29, x30, \[sp, 128\] ** add x29, sp, #?128 -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl128 ** add sp, sp, #?16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?128 ** ldp x29, x30, \[sp\] ** mov x12, #?4112 @@ -157,7 +157,7 @@ test_7 (void) { volatile int x[1024]; take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -169,12 +169,12 @@ test_7 (void) ** add x29, sp, #?128 ** stp x24, x25, \[sp, 144\] ** str x26, \[sp, 160\] -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl128 ** add sp, sp, #?16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?128 ** ldp x24, x25, \[sp, 16\] ** ldr x26, \[sp, 32\] @@ -188,7 +188,7 @@ test_8 (void) { volatile int x[1024]; take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } @@ -198,12 +198,12 @@ test_8 (void) ** sub sp, sp, x12 ** stp x29, x30, \[sp, 128\] ** add x29, sp, #?128 -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl128 ** sub sp, x29, #128 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?128 ** ldp x29, x30, \[sp\] ** mov x12, #?4112 @@ -215,7 +215,7 @@ test_9 (int n) { volatile int x[1024]; take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -227,12 +227,12 @@ test_9 (int n) ** add x29, sp, #?128 ** stp x24, x25, \[sp, 144\] ** str x26, \[sp, 160\] -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl128 ** sub sp, x29, #128 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?128 ** ldp x24, x25, \[sp, 16\] ** ldr x26, \[sp, 32\] @@ -246,7 +246,7 @@ test_10 (int n) { volatile int x[1024]; take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } @@ -261,12 +261,12 @@ test_10 (int n) ** add x29, sp, #?128 ** stp x24, x25, \[sp, 144\] ** str x26, \[sp, 160\] -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl128 ** sub sp, x29, #128 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?128 ** ldp x24, x25, \[sp, 16\] ** ldr x26, \[sp, 32\] @@ -280,6 +280,6 @@ test_11 (int n) { volatile int x[0x7ee4]; take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_2048.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_2048.c index c185e2e3628..f63751678e5 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_2048.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_2048.c @@ -10,10 +10,10 @@ svbool_t take_stack_args (volatile void *, void *, int, int, int, /* ** test_1: ** sub sp, sp, #272 -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl256 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?272 ** ret */ @@ -21,7 +21,7 @@ svbool_t test_1 (void) { volatile int x = 1; - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -30,10 +30,10 @@ test_1 (void) ** sub sp, sp, #304 ** stp x24, x25, \[sp, 256\] ** str x26, \[sp, 272\] -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl256 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** ldp x24, x25, \[sp, 256\] ** ldr x26, \[sp, 272\] ** add sp, sp, #?304 @@ -43,7 +43,7 @@ svbool_t test_2 (void) { volatile int x = 1; - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } @@ -53,10 +53,10 @@ test_2 (void) ** sub sp, sp, x12 ** stp x24, x25, \[sp, 256\] ** str x26, \[sp, 272\] -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl256 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** ldp x24, x25, \[sp, 256\] ** ldr x26, \[sp, 272\] ** add sp, sp, x12 @@ -66,17 +66,17 @@ svbool_t test_3 (void) { volatile int x[1024]; - asm volatile ("" :: "r" (x) : "p4", "x24", "x25", "x26"); + asm volatile ("" :: "r" (x) : "z16", "x24", "x25", "x26"); return svptrue_b8 (); } /* ** test_4: ** sub sp, sp, #512 -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.h, vl128 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?512 ** ret */ @@ -85,7 +85,7 @@ test_4 (void) { volatile svint32_t b; b = svdup_s32 (1); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b16 (); } @@ -94,10 +94,10 @@ test_4 (void) ** sub sp, sp, #544 ** stp x24, x25, \[sp, 256\] ** str x26, \[sp, 272\] -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.h, vl128 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** ldp x24, x25, \[sp, 256\] ** ldr x26, \[sp, 272\] ** add sp, sp, #?544 @@ -108,7 +108,7 @@ test_5 (void) { volatile svint32_t b; b = svdup_s32 (1); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b16 (); } @@ -117,11 +117,11 @@ test_5 (void) ** stp x29, x30, \[sp, -16\]! ** mov x29, sp ** sub sp, sp, #256 -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl256 ** add sp, sp, #?16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?256 ** ldp x29, x30, \[sp\], 16 ** ret @@ -130,7 +130,7 @@ svbool_t test_6 (void) { take_stack_args (0, 0, 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -140,12 +140,12 @@ test_6 (void) ** sub sp, sp, x12 ** stp x29, x30, \[sp, 256\] ** add x29, sp, #?256 -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl256 ** add sp, sp, #?16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?256 ** ldp x29, x30, \[sp\] ** mov x12, #?4112 @@ -157,7 +157,7 @@ test_7 (void) { volatile int x[1024]; take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -169,12 +169,12 @@ test_7 (void) ** add x29, sp, #?256 ** stp x24, x25, \[sp, 272\] ** str x26, \[sp, 288\] -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl256 ** add sp, sp, #?16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?256 ** ldp x24, x25, \[sp, 16\] ** ldr x26, \[sp, 32\] @@ -188,7 +188,7 @@ test_8 (void) { volatile int x[1024]; take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } @@ -198,12 +198,12 @@ test_8 (void) ** sub sp, sp, x12 ** stp x29, x30, \[sp, 256\] ** add x29, sp, #?256 -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl256 ** sub sp, x29, #256 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?256 ** ldp x29, x30, \[sp\] ** mov x12, #?4112 @@ -215,7 +215,7 @@ test_9 (int n) { volatile int x[1024]; take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -227,12 +227,12 @@ test_9 (int n) ** add x29, sp, #?256 ** stp x24, x25, \[sp, 272\] ** str x26, \[sp, 288\] -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl256 ** sub sp, x29, #256 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?256 ** ldp x24, x25, \[sp, 16\] ** ldr x26, \[sp, 32\] @@ -246,7 +246,7 @@ test_10 (int n) { volatile int x[1024]; take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } @@ -261,12 +261,12 @@ test_10 (int n) ** add x29, sp, #?256 ** stp x24, x25, \[sp, 272\] ** str x26, \[sp, 288\] -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl256 ** sub sp, x29, #256 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?256 ** ldp x24, x25, \[sp, 16\] ** ldr x26, \[sp, 32\] @@ -280,6 +280,6 @@ test_11 (int n) { volatile int x[0x7ee4]; take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_256.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_256.c index f8318b354a0..6bcbb57725b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_256.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_256.c @@ -10,10 +10,10 @@ svbool_t take_stack_args (volatile void *, void *, int, int, int, /* ** test_1: ** sub sp, sp, #48 -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl32 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?48 ** ret */ @@ -21,7 +21,7 @@ svbool_t test_1 (void) { volatile int x = 1; - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -30,10 +30,10 @@ test_1 (void) ** sub sp, sp, #80 ** stp x24, x25, \[sp, 32\] ** str x26, \[sp, 48\] -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl32 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** ldp x24, x25, \[sp, 32\] ** ldr x26, \[sp, 48\] ** add sp, sp, #?80 @@ -43,7 +43,7 @@ svbool_t test_2 (void) { volatile int x = 1; - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } @@ -53,10 +53,10 @@ test_2 (void) ** sub sp, sp, x12 ** stp x24, x25, \[sp, 32\] ** str x26, \[sp, 48\] -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl32 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** ldp x24, x25, \[sp, 32\] ** ldr x26, \[sp, 48\] ** add sp, sp, x12 @@ -66,17 +66,17 @@ svbool_t test_3 (void) { volatile int x[1024]; - asm volatile ("" :: "r" (x) : "p4", "x24", "x25", "x26"); + asm volatile ("" :: "r" (x) : "z16", "x24", "x25", "x26"); return svptrue_b8 (); } /* ** test_4: ** sub sp, sp, #64 -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.h, vl16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?64 ** ret */ @@ -85,7 +85,7 @@ test_4 (void) { volatile svint32_t b; b = svdup_s32 (1); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b16 (); } @@ -94,10 +94,10 @@ test_4 (void) ** sub sp, sp, #96 ** stp x24, x25, \[sp, 32\] ** str x26, \[sp, 48\] -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.h, vl16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** ldp x24, x25, \[sp, 32\] ** ldr x26, \[sp, 48\] ** add sp, sp, #?96 @@ -108,7 +108,7 @@ test_5 (void) { volatile svint32_t b; b = svdup_s32 (1); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b16 (); } @@ -117,11 +117,11 @@ test_5 (void) ** stp x29, x30, \[sp, -16\]! ** mov x29, sp ** sub sp, sp, #32 -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl32 ** add sp, sp, #?16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?32 ** ldp x29, x30, \[sp\], 16 ** ret @@ -130,7 +130,7 @@ svbool_t test_6 (void) { take_stack_args (0, 0, 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -140,12 +140,12 @@ test_6 (void) ** sub sp, sp, x12 ** stp x29, x30, \[sp, 32\] ** add x29, sp, #?32 -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl32 ** add sp, sp, #?16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?32 ** ldp x29, x30, \[sp\] ** mov x12, #?4112 @@ -157,7 +157,7 @@ test_7 (void) { volatile int x[1024]; take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -169,12 +169,12 @@ test_7 (void) ** add x29, sp, #?32 ** stp x24, x25, \[sp, 48\] ** str x26, \[sp, 64\] -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl32 ** add sp, sp, #?16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?32 ** ldp x24, x25, \[sp, 16\] ** ldr x26, \[sp, 32\] @@ -188,7 +188,7 @@ test_8 (void) { volatile int x[1024]; take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } @@ -198,12 +198,12 @@ test_8 (void) ** sub sp, sp, x12 ** stp x29, x30, \[sp, 32\] ** add x29, sp, #?32 -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl32 ** sub sp, x29, #32 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?32 ** ldp x29, x30, \[sp\] ** mov x12, #?4112 @@ -215,7 +215,7 @@ test_9 (int n) { volatile int x[1024]; take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -227,12 +227,12 @@ test_9 (int n) ** add x29, sp, #?32 ** stp x24, x25, \[sp, 48\] ** str x26, \[sp, 64\] -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl32 ** sub sp, x29, #32 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?32 ** ldp x24, x25, \[sp, 16\] ** ldr x26, \[sp, 32\] @@ -246,7 +246,7 @@ test_10 (int n) { volatile int x[1024]; take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } @@ -260,12 +260,12 @@ test_10 (int n) ** add x29, sp, #?32 ** stp x24, x25, \[sp, 48\] ** str x26, \[sp, 64\] -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl32 ** sub sp, x29, #32 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?32 ** ldp x24, x25, \[sp, 16\] ** ldr x26, \[sp, 32\] @@ -279,6 +279,6 @@ test_11 (int n) { volatile int x[0x7ee4]; take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_512.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_512.c index 45a23ad4909..dc7df8e6bf7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_512.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_512.c @@ -10,10 +10,10 @@ svbool_t take_stack_args (volatile void *, void *, int, int, int, /* ** test_1: ** sub sp, sp, #80 -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl64 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?80 ** ret */ @@ -21,7 +21,7 @@ svbool_t test_1 (void) { volatile int x = 1; - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -30,10 +30,10 @@ test_1 (void) ** sub sp, sp, #112 ** stp x24, x25, \[sp, 64\] ** str x26, \[sp, 80\] -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl64 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** ldp x24, x25, \[sp, 64\] ** ldr x26, \[sp, 80\] ** add sp, sp, #?112 @@ -43,7 +43,7 @@ svbool_t test_2 (void) { volatile int x = 1; - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } @@ -53,10 +53,10 @@ test_2 (void) ** sub sp, sp, x12 ** stp x24, x25, \[sp, 64\] ** str x26, \[sp, 80\] -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl64 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** ldp x24, x25, \[sp, 64\] ** ldr x26, \[sp, 80\] ** add sp, sp, x12 @@ -66,17 +66,17 @@ svbool_t test_3 (void) { volatile int x[1024]; - asm volatile ("" :: "r" (x) : "p4", "x24", "x25", "x26"); + asm volatile ("" :: "r" (x) : "z16", "x24", "x25", "x26"); return svptrue_b8 (); } /* ** test_4: ** sub sp, sp, #128 -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.h, vl32 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?128 ** ret */ @@ -85,7 +85,7 @@ test_4 (void) { volatile svint32_t b; b = svdup_s32 (1); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b16 (); } @@ -94,10 +94,10 @@ test_4 (void) ** sub sp, sp, #160 ** stp x24, x25, \[sp, 64\] ** str x26, \[sp, 80\] -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.h, vl32 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** ldp x24, x25, \[sp, 64\] ** ldr x26, \[sp, 80\] ** add sp, sp, #?160 @@ -108,7 +108,7 @@ test_5 (void) { volatile svint32_t b; b = svdup_s32 (1); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b16 (); } @@ -117,11 +117,11 @@ test_5 (void) ** stp x29, x30, \[sp, -16\]! ** mov x29, sp ** sub sp, sp, #64 -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl64 ** add sp, sp, #?16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?64 ** ldp x29, x30, \[sp\], 16 ** ret @@ -130,7 +130,7 @@ svbool_t test_6 (void) { take_stack_args (0, 0, 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -140,12 +140,12 @@ test_6 (void) ** sub sp, sp, x12 ** stp x29, x30, \[sp, 64\] ** add x29, sp, #?64 -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl64 ** add sp, sp, #?16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?64 ** ldp x29, x30, \[sp\] ** mov x12, #?4112 @@ -157,7 +157,7 @@ test_7 (void) { volatile int x[1024]; take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -169,12 +169,12 @@ test_7 (void) ** add x29, sp, #?64 ** stp x24, x25, \[sp, 80\] ** str x26, \[sp, 96\] -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl64 ** add sp, sp, #?16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?64 ** ldp x24, x25, \[sp, 16\] ** ldr x26, \[sp, 32\] @@ -188,7 +188,7 @@ test_8 (void) { volatile int x[1024]; take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } @@ -198,12 +198,12 @@ test_8 (void) ** sub sp, sp, x12 ** stp x29, x30, \[sp, 64\] ** add x29, sp, #?64 -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl64 ** sub sp, x29, #64 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?64 ** ldp x29, x30, \[sp\] ** mov x12, #?4112 @@ -215,7 +215,7 @@ test_9 (int n) { volatile int x[1024]; take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -227,12 +227,12 @@ test_9 (int n) ** add x29, sp, #?64 ** stp x24, x25, \[sp, 80\] ** str x26, \[sp, 96\] -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl64 ** sub sp, x29, #64 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?64 ** ldp x24, x25, \[sp, 16\] ** ldr x26, \[sp, 32\] @@ -246,7 +246,7 @@ test_10 (int n) { volatile int x[1024]; take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } @@ -261,12 +261,12 @@ test_10 (int n) ** add x29, sp, #?64 ** stp x24, x25, \[sp, 80\] ** str x26, \[sp, 96\] -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl64 ** sub sp, x29, #64 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?64 ** ldp x24, x25, \[sp, 16\] ** ldr x26, \[sp, 32\] @@ -280,6 +280,6 @@ test_11 (int n) { volatile int x[0x7ee4]; take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } -- 2.30.2