From cb27e2b2898214d55da4a26bffcf70e77c0b45b2 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 2 Jul 2018 09:36:49 +0100 Subject: [PATCH] add input tests --- src/test_bsv/tests/test_pinmux.py | 36 ++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/src/test_bsv/tests/test_pinmux.py b/src/test_bsv/tests/test_pinmux.py index 851191b..a3aa80c 100644 --- a/src/test_bsv/tests/test_pinmux.py +++ b/src/test_bsv/tests/test_pinmux.py @@ -21,7 +21,7 @@ def pinmux_basic_test(dut): yield Timer(2) - # GPIO + # GPIO2-out test dut.peripheral_side_gpioa_a2_out_in = 0 dut.peripheral_side_gpioa_a2_outen_in = 1 @@ -36,6 +36,40 @@ def pinmux_basic_test(dut): yield Timer(2) + if dut.iocell_side_io2_cell_out != 1: + raise TestFailure( + "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 1" % \ + str(dut.iocell_side_io2_cell_out )) + + # GPIO2-in test (first see if it's tri-state) + if str(dut.peripheral_side_gpioa_a2_in) != "x": + raise TestFailure( + "gpioa_a2=0/mux=0/out=1 %s gpio_a2_in != x" % \ + str(dut.peripheral_side_gpioa_a2_in)) + + dut.peripheral_side_gpioa_a2_outen_in = 0 + dut.iocell_side_io2_cell_in_in = 0 + yield Timer(2) + + if dut.peripheral_side_gpioa_a2_in != 0: + raise TestFailure( + "iocell_io2=0/mux=0/out=0 %s gpioa_a2 != 0" % \ + str(dut.peripheral_side_gpioa_a2_in)) + + dut.iocell_side_io2_cell_in_in = 1 + yield Timer(2) + + if dut.peripheral_side_gpioa_a2_in != 1: + raise TestFailure( + "iocell_io2=1/mux=0/out=0 %s gpioa_a2 != 1" % \ + str(dut.peripheral_side_gpioa_a2_in)) + + dut.peripheral_side_gpioa_a2_outen_in = 1 + dut.iocell_side_io2_cell_in_in = 0 + yield Timer(2) + dut._log.info("gpioa_a2_in %s" % dut.peripheral_side_gpioa_a2_in ) + + if dut.iocell_side_io2_cell_out != 1: raise TestFailure( "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 1" % \ -- 2.30.2