From cb4b152d88b9c77f552345917601d401010dc4b3 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Thu, 21 Dec 2017 20:00:28 +0100 Subject: [PATCH] re PR target/83467 (ICE: in assign_by_spills, at lra-assigns.c:1476: unable to find a register to spill with -flive-range-shrinkage -m8bit-idiv) PR target/83467 * config/i386/i386.md (*ashl3_mask): Add operand constraints to operand 2. (*ashl3_mask_1): Ditto. (*3_mask): Ditto. (*3_mask_1): Ditto. (*3_mask): Ditto. (*3_mask_1): Ditto. testsuite/ChangeLog: PR target/83467 * gcc.target/i386/pr83467-1.c: New test. * gcc.target/i386/pr83467-2.c: Ditto. From-SVN: r255949 --- gcc/ChangeLog | 57 ++++++++++++++--------- gcc/config/i386/i386.md | 26 +++++++---- gcc/testsuite/ChangeLog | 10 +++- gcc/testsuite/gcc.target/i386/pr83467-1.c | 18 +++++++ gcc/testsuite/gcc.target/i386/pr83467-2.c | 13 ++++++ 5 files changed, 90 insertions(+), 34 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr83467-1.c create mode 100644 gcc/testsuite/gcc.target/i386/pr83467-2.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7200561a332..7f9d16c08d3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,9 +1,19 @@ -2017-12-21 Alexandre Oliva +2017-12-21 Uros Bizjak - * reorg.c (make_return_insns): Reemit each insn with its own - location. + PR target/83467 + * config/i386/i386.md (*ashl3_mask): Add operand + constraints to operand 2. + (*ashl3_mask_1): Ditto. + (*3_mask): Ditto. + (*3_mask_1): Ditto. + (*3_mask): Ditto. + (*3_mask_1): Ditto. -2017-12-21 Alexandre Oliva +2017-12-21 Alexandre Oliva + + * reorg.c (make_return_insns): Reemit each insn with its own location. + +2017-12-21 Alexandre Oliva PR debug/83419 * c-family/c-semantics.c (pop_stmt_list): Propagate side @@ -631,7 +641,7 @@ (expand_builtin_strcmp): Call maybe_warn_nonstring_arg. (expand_builtin_strncmp): Same. -2017-12-20 Alexandre Oliva +2017-12-20 Alexandre Oliva PR bootstrap/83396 * cfgexpand.c (label_rtx_for_bb): Revert SFN changes that @@ -1290,7 +1300,7 @@ poly_int64. Use strip_offset_and_add to handle (plus X (const)). 2017-12-20 Richard Sandiford - Alan Hayward + Alan Hayward David Sherwood * rtl.h (reg_attrs::offset): Change from HOST_WIDE_INT to poly_int64. @@ -1317,7 +1327,7 @@ of a PARALLEL. 2017-12-20 Richard Sandiford - Alan Hayward + Alan Hayward David Sherwood * target.def (truly_noop_truncation): Take poly_uint64s instead of @@ -1606,7 +1616,8 @@ 2017-12-20 Tom de Vries PR middle-end/83423 - * config/i386/i386.c (ix86_static_chain): Move DECL_STATIC_CHAIN test ... + * config/i386/i386.c (ix86_static_chain): Move + DECL_STATIC_CHAIN test ... * calls.c (rtx_for_static_chain): ... here. New function. * calls.h (rtx_for_static_chain): Declare. * builtins.c (expand_builtin_setjmp_receiver): Use rtx_for_static_chain @@ -1642,7 +1653,7 @@ character load case, if get_stridx on MEM_REF's operand doesn't look usable, retry with get_addr_stridx. -2017-12-19 Alexandre Oliva +2017-12-19 Alexandre Oliva PR debug/83422 * var-tracking.c (vt_debug_insns_local): Do not drop markers. @@ -1712,7 +1723,8 @@ * sched-rgn.c (sched_rgn_init): Likewise. * diagnostic-show-locus.c (layout::show_ruler): Likewise. * combine.c (find_split_point, simplify_if_then_else, force_to_mode, - if_then_else_cond, simplify_shift_const_1, simplify_comparison): Likewise. + if_then_else_cond, simplify_shift_const_1, simplify_comparison): + Likewise. * explow.c (eliminate_constant_term): Likewise. * final.c (leaf_renumber_regs_insn): Likewise. * cfgrtl.c (print_rtl_with_bb): Likewise. @@ -1762,7 +1774,7 @@ PR c++/83489 * config/i386/i386.c (init_cumulative_args): Don't check TYPE_EMPTY_P - on an error node. + on an error node. 2017-12-19 Claudiu Zissulescu @@ -1881,9 +1893,9 @@ * doc/extend.texi (x86 Function Attributes): Reformat nocf_check example to avoid overfull hbox. * doc/invoke.texi (Option Summary): Add missing @gol. - (C++ Dialect Options): Reformat -Wnoexcept-type example to avoid + (C++ Dialect Options): Reformat -Wnoexcept-type example to avoid overfull hbox. - + 2017-12-17 Sandra Loosemore Kyrylo Tkachov @@ -2211,13 +2223,13 @@ optimizing for size. Don't pessimize blocks which will be copied, but all the statements will be dead. -2017-12-15 Alexandre Oliva +2017-12-15 Alexandre Oliva PR tree-optimization/81165 * tree-ssa-threadupdate.c (uses_in_bb): New. (estimate_threading_killed_stmts): New. * tree-ssa-threadupdate.h (estimate_threading_killed_stmts): Prototype. - * tree-ssa-threadedge.c + * tree-ssa-threadedge.c (record_temporary_equivalences_from_stmts_at_dest): Expand limit when its hit. @@ -2343,7 +2355,8 @@ 2017-12-15 Julia Koval * config/i386/i386-builtin.def (__builtin_ia32_vaesenclast_v16qi, - __builtin_ia32_vaesenclast_v32qi, __builtin_ia32_vaesenclast_v64qi): New. + __builtin_ia32_vaesenclast_v32qi, __builtin_ia32_vaesenclast_v64qi): + New. * config/i386/sse.md (vaesenclast_): New pattern. * config/i386/vaesintrin.h (_mm256_aesenclast_epi128, _mm512_aesenclast_epi128, _mm_aesenclast_epi128): New intrinsics. @@ -2359,7 +2372,8 @@ 2017-12-15 Julia Koval * config/i386/i386-builtin.def (__builtin_ia32_vaesdeclast_v16qi, - __builtin_ia32_vaesdeclast_v32qi, __builtin_ia32_vaesdeclast_v64qi): New. + __builtin_ia32_vaesdeclast_v32qi, __builtin_ia32_vaesdeclast_v64qi): + New. * config/i386/sse.md (vaesdeclast_): New pattern. * config/i386/vaesintrin.h (_mm256_aesdeclast_epi128, _mm512_aesdeclast_epi128, _mm_aesdeclast_epi128): New intrinsics. @@ -2415,7 +2429,7 @@ PR bootstrap/83396 * reload1.c (emit_input_reload_insns): Skip debug markers. -2017-12-14 Alexandre Oliva +2017-12-14 Alexandre Oliva * config/i386/i386.c (rest_of_insert_endbranch): Use call loc for its nop_endbr. @@ -2453,8 +2467,7 @@ PR tree-optimization/83418 * vr-values.c (vr_values::extract_range_for_var_from_comparison_expr): - Instead of asserting we don't get unfolded comparisons deal with - them. + Instead of asserting we don't get unfolded comparisons deal with them. 2017-12-14 Jakub Jelinek @@ -2518,7 +2531,7 @@ (ASSERT_MAYBE_NE_AT): New macros. 2017-12-13 Eric Botcazou - Dominik Vogt + Dominik Vogt PR middle-end/78468 * emit-rtl.c (init_emit): Remove ??? comment. @@ -2534,7 +2547,7 @@ * config/rs6000/ppc-auxv.h (PPC_FEATURE2_HTM_NO_SUSPEND): New define. * config/rs6000/rs6000.c (cpu_supports_info): Use it. -2017-12-13 Alexandre Oliva +2017-12-13 Alexandre Oliva PR bootstrap/83396 * reload1.c (eliminate_regs_in_insn): Skip debug markers. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index c6ab79a42ac..59d9245234f 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -10353,7 +10353,7 @@ (match_operand:SWI48 1 "nonimmediate_operand") (subreg:QI (and:SI - (match_operand:SI 2 "register_operand") + (match_operand:SI 2 "register_operand" "c,r") (match_operand:SI 3 "const_int_operand")) 0))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ASHIFT, mode, operands) @@ -10367,14 +10367,15 @@ (ashift:SWI48 (match_dup 1) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] - "operands[2] = gen_lowpart (QImode, operands[2]);") + "operands[2] = gen_lowpart (QImode, operands[2]);" + [(set_attr "isa" "*,bmi2")]) (define_insn_and_split "*ashl3_mask_1" [(set (match_operand:SWI48 0 "nonimmediate_operand") (ashift:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") (and:QI - (match_operand:QI 2 "register_operand") + (match_operand:QI 2 "register_operand" "c,r") (match_operand:QI 3 "const_int_operand")))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ASHIFT, mode, operands) @@ -10387,7 +10388,9 @@ [(set (match_dup 0) (ashift:SWI48 (match_dup 1) (match_dup 2))) - (clobber (reg:CC FLAGS_REG))])]) + (clobber (reg:CC FLAGS_REG))])] + "" + [(set_attr "isa" "*,bmi2")]) (define_insn "*bmi2_ashl3_1" [(set (match_operand:SWI48 0 "register_operand" "=r") @@ -10873,7 +10876,7 @@ (match_operand:SWI48 1 "nonimmediate_operand") (subreg:QI (and:SI - (match_operand:SI 2 "register_operand") + (match_operand:SI 2 "register_operand" "c,r") (match_operand:SI 3 "const_int_operand")) 0))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (, mode, operands) @@ -10887,14 +10890,15 @@ (any_shiftrt:SWI48 (match_dup 1) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] - "operands[2] = gen_lowpart (QImode, operands[2]);") + "operands[2] = gen_lowpart (QImode, operands[2]);" + [(set_attr "isa" "*,bmi2")]) (define_insn_and_split "*3_mask_1" [(set (match_operand:SWI48 0 "nonimmediate_operand") (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") (and:QI - (match_operand:QI 2 "register_operand") + (match_operand:QI 2 "register_operand" "c,r") (match_operand:QI 3 "const_int_operand")))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (, mode, operands) @@ -10907,7 +10911,9 @@ [(set (match_dup 0) (any_shiftrt:SWI48 (match_dup 1) (match_dup 2))) - (clobber (reg:CC FLAGS_REG))])]) + (clobber (reg:CC FLAGS_REG))])] + "" + [(set_attr "isa" "*,bmi2")]) (define_insn_and_split "*3_doubleword" [(set (match_operand:DWI 0 "register_operand" "=&r") @@ -11352,7 +11358,7 @@ (match_operand:SWI48 1 "nonimmediate_operand") (subreg:QI (and:SI - (match_operand:SI 2 "register_operand") + (match_operand:SI 2 "register_operand" "c") (match_operand:SI 3 "const_int_operand")) 0))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (, mode, operands) @@ -11373,7 +11379,7 @@ (any_rotate:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") (and:QI - (match_operand:QI 2 "register_operand") + (match_operand:QI 2 "register_operand" "c") (match_operand:QI 3 "const_int_operand")))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (, mode, operands) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 8cc163adac0..2696f5e8655 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,4 +1,10 @@ -2017-12-21 Alexandre Oliva +2017-12-21 Uros Bizjak + + PR target/83467 + * gcc.target/i386/pr83467-1.c: New test. + * gcc.target/i386/pr83467-2.c: Ditto. + +2017-12-21 Alexandre Oliva PR debug/83419 * gcc.dg/pr83419.c: New. @@ -111,7 +117,7 @@ * gcc.dg/Wstringop-overflow.c: New test. * gcc/testsuite/c-c++-common/Warray-bounds-3.c: Adjust. -2017-12-19 Alexandre Oliva +2017-12-19 Alexandre Oliva PR debug/83422 * gcc.dg/pr83422.c: New. diff --git a/gcc/testsuite/gcc.target/i386/pr83467-1.c b/gcc/testsuite/gcc.target/i386/pr83467-1.c new file mode 100644 index 00000000000..b5cf17edec2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr83467-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -flive-range-shrinkage -m8bit-idiv" } */ +/* { dg-require-effective-target int128 } */ + +unsigned a; + +__int128 +b (unsigned c, short d, int e, long f, unsigned __int128 g, char h, + int i, __int128 j) +{ + j %= 5; + c *= i; + e = e >> (g & 31); + h &= e /= d; + g <<= 0 <= 0; + g &= h < j; + return c + d + f + g + h + i + a + j; +} diff --git a/gcc/testsuite/gcc.target/i386/pr83467-2.c b/gcc/testsuite/gcc.target/i386/pr83467-2.c new file mode 100644 index 00000000000..1b424fec2cb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr83467-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -flive-range-shrinkage" } */ +/* { dg-require-effective-target int128 } */ + +int +a (int b, short c, int d, long e, __int128 f, short g, long h, __int128 i) +{ + d <<= f & 31; + f >>= 127; + g *= d > c; + f >>= g; + return b + e + f + h + i; +} -- 2.30.2