From cb5e0953aa3552c8d2fad507ec6b6994deaafcc9 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Robert=20J=C3=B6rdens?= Date: Fri, 29 Nov 2013 01:47:32 -0700 Subject: [PATCH] migen/test: start unittests --- migen/test/__init__.py | 0 migen/test/support.py | 24 ++++++++++++++++++++++++ setup.py | 1 + 3 files changed, 25 insertions(+) create mode 100644 migen/test/__init__.py create mode 100644 migen/test/support.py diff --git a/migen/test/__init__.py b/migen/test/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/migen/test/support.py b/migen/test/support.py new file mode 100644 index 00000000..016373d7 --- /dev/null +++ b/migen/test/support.py @@ -0,0 +1,24 @@ +import unittest +from migen.fhdl.std import * +from migen.sim.generic import Simulator +from migen.fhdl import verilog + +class SimBench(Module): + callback = None + def do_simulation(self, s): + if self.callback is not None: + return self.callback(self, s) + +class SimCase(unittest.TestCase): + TestBench = SimBench + + def setUp(self): + self.tb = self.TestBench() + + def test_to_verilog(self): + verilog.convert(self.tb) + + def run_with(self, cb, cycles=-1): + self.tb.callback = cb + with Simulator(self.tb) as s: + s.run(cycles) diff --git a/setup.py b/setup.py index 61121f1a..3c6713fd 100755 --- a/setup.py +++ b/setup.py @@ -22,6 +22,7 @@ setup( url="http://www.milkymist.org", download_url="https://github.com/milkymist/migen", packages=find_packages(here), + test_suite="migen.test", license="BSD", platforms=["Any"], keywords="HDL ASIC FPGA hardware design", -- 2.30.2