From cb81618c28d9cbcf1713bbcf632c740a12b30d45 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 26 Aug 2020 04:15:26 +0000 Subject: [PATCH] sim._pyrtl: fix miscompilation of -(Const(0b11, 2).as_signed()). Fixes #473. --- nmigen/sim/_pyrtl.py | 2 +- nmigen/test/test_sim.py | 8 ++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/nmigen/sim/_pyrtl.py b/nmigen/sim/_pyrtl.py index 9c7225a..c2e9367 100644 --- a/nmigen/sim/_pyrtl.py +++ b/nmigen/sim/_pyrtl.py @@ -116,7 +116,7 @@ class _RHSValueCompiler(_ValueCompiler): if value.operator == "~": return f"(~{self(arg)})" if value.operator == "-": - return f"(-{self(arg)})" + return f"(-{sign(arg)})" if value.operator == "b": return f"bool({mask(arg)})" if value.operator == "r|": diff --git a/nmigen/test/test_sim.py b/nmigen/test/test_sim.py index 8626e71..94424f7 100644 --- a/nmigen/test/test_sim.py +++ b/nmigen/test/test_sim.py @@ -365,6 +365,7 @@ class SimulatorUnitTestCase(FHDLTestCase): self.assertStatement(stmt, [C(0b1000000)], C(0b0000010)) self.assertStatement(stmt, [C(0b1000001)], C(0b0000110)) + class SimulatorIntegrationTestCase(FHDLTestCase): @contextmanager def assertSimulation(self, module, deadline=None): @@ -788,3 +789,10 @@ class SimulatorRegressionTestCase(FHDLTestCase): dut = Module() dut.d.comb += Signal().eq(Repl(Const(1), 0)) Simulator(dut).run() + + def test_bug_473(self): + sim = Simulator(Module()) + def process(): + self.assertEqual((yield -(Const(0b11, 2).as_signed())), 1) + sim.add_process(process) + sim.run() -- 2.30.2