From cb8be4a1b0f7302150b38259b0d04a65a4d6e89f Mon Sep 17 00:00:00 2001 From: whitequark Date: Sun, 7 Jul 2019 00:59:57 +0000 Subject: [PATCH] hdl.dsl: clarify error message for incorrect nesting. Refs #133. --- nmigen/hdl/dsl.py | 2 +- nmigen/test/test_hdl_dsl.py | 12 +++++++++++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/nmigen/hdl/dsl.py b/nmigen/hdl/dsl.py index 415ad95..a2cec0b 100644 --- a/nmigen/hdl/dsl.py +++ b/nmigen/hdl/dsl.py @@ -133,7 +133,7 @@ class Module(_ModuleBuilderRoot, Elaboratable): raise SyntaxError("{} is not permitted outside of {}" .format(construct, context)) else: - raise SyntaxError("{} is not permitted inside of {}" + raise SyntaxError("{} is not permitted directly inside of {}" .format(construct, self._ctrl_context)) def _get_ctrl(self, name): diff --git a/nmigen/test/test_hdl_dsl.py b/nmigen/test/test_hdl_dsl.py index 714eb47..e01b083 100644 --- a/nmigen/test/test_hdl_dsl.py +++ b/nmigen/test/test_hdl_dsl.py @@ -345,7 +345,7 @@ class DSLTestCase(FHDLTestCase): m = Module() with m.Switch(self.s1): with self.assertRaises(SyntaxError, - msg="If is not permitted inside of Switch"): + msg="If is not permitted directly inside of Switch"): with m.If(self.s2): pass @@ -480,6 +480,16 @@ class DSLTestCase(FHDLTestCase): with m.FSM(): m.next = "FOO" + def test_If_inside_FSM_wrong(self): + m = Module() + with m.FSM(): + with m.State("FOO"): + pass + with self.assertRaises(SyntaxError, + msg="If is not permitted directly inside of FSM"): + with m.If(self.s2): + pass + def test_auto_pop_ctrl(self): m = Module() with m.If(self.w1): -- 2.30.2