From cb8c26d1b8421828e6ecac72ff3705313a504414 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 21 Apr 2019 00:17:03 +0200 Subject: [PATCH] boards/platforms: provide only one default programmer per platform. create_programmer is not really longer used, so try to keep it simple. --- litex/boards/platforms/arty.py | 14 +++----------- litex/boards/platforms/genesys2.py | 8 ++------ litex/boards/platforms/kc705.py | 3 +-- litex/boards/platforms/kcu105.py | 3 +-- litex/boards/platforms/minispartan6.py | 11 ++--------- litex/boards/platforms/nexys4ddr.py | 12 ++---------- litex/boards/platforms/nexys_video.py | 14 +++----------- litex/boards/platforms/tinyfpga_bx.py | 3 +-- 8 files changed, 15 insertions(+), 53 deletions(-) diff --git a/litex/boards/platforms/arty.py b/litex/boards/platforms/arty.py index 48c9c487..7a84287a 100644 --- a/litex/boards/platforms/arty.py +++ b/litex/boards/platforms/arty.py @@ -233,22 +233,14 @@ class Platform(XilinxPlatform): default_clk_name = "clk100" default_clk_period = 10.0 - def __init__(self, toolchain="vivado", programmer="vivado"): - XilinxPlatform.__init__(self, "xc7a35ticsg324-1L", _io, _connectors, - toolchain=toolchain) + def __init__(self): + XilinxPlatform.__init__(self, "xc7a35ticsg324-1L", _io, _connectors, toolchain="vivado") self.toolchain.bitstream_commands = \ ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] self.toolchain.additional_commands = \ ["write_cfgmem -force -format bin -interface spix4 -size 16 " "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] - self.programmer = programmer self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]") def create_programmer(self): - if self.programmer == "xc3sprog": - return XC3SProg("nexys4") - elif self.programmer == "vivado": - return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4") - else: - raise ValueError("{} programmer is not supported" - .format(self.programmer)) + return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4") diff --git a/litex/boards/platforms/genesys2.py b/litex/boards/platforms/genesys2.py index 083ab085..8f8b1de1 100644 --- a/litex/boards/platforms/genesys2.py +++ b/litex/boards/platforms/genesys2.py @@ -105,15 +105,11 @@ class Platform(XilinxPlatform): default_clk_name = "clk200" default_clk_period = 5 - def __init__(self, programmer="vivado"): + def __init__(self): XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado") - self.programmer = programmer def create_programmer(self): - if self.programmer == "vivado": - return VivadoProgrammer() - else: - raise ValueError("{} programmer is not supported".format(programmer)) + return VivadoProgrammer() def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex/boards/platforms/kc705.py b/litex/boards/platforms/kc705.py index 7a30df20..fea45a8b 100644 --- a/litex/boards/platforms/kc705.py +++ b/litex/boards/platforms/kc705.py @@ -526,7 +526,7 @@ class Platform(XilinxPlatform): default_clk_name = "clk156" default_clk_period = 6.4 - def __init__(self, programmer="vivado"): + def __init__(self): XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado") self.add_platform_command(""" set_property CFGBVS VCCO [current_design] @@ -534,7 +534,6 @@ set_property CONFIG_VOLTAGE 2.5 [current_design] """) self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] - self.programmer = programmer def create_programmer(self): if self.programmer == "xc3sprog": diff --git a/litex/boards/platforms/kcu105.py b/litex/boards/platforms/kcu105.py index 2ea7c5c0..c98aaf82 100644 --- a/litex/boards/platforms/kcu105.py +++ b/litex/boards/platforms/kcu105.py @@ -482,8 +482,7 @@ class Platform(XilinxPlatform): default_clk_period = 8.0 def __init__(self): - XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, _connectors, - toolchain="vivado") + XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, _connectors, toolchain="vivado") def create_programmer(self): return VivadoProgrammer() diff --git a/litex/boards/platforms/minispartan6.py b/litex/boards/platforms/minispartan6.py index d22e9553..e2cdfd2a 100644 --- a/litex/boards/platforms/minispartan6.py +++ b/litex/boards/platforms/minispartan6.py @@ -113,15 +113,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk32" default_clk_period = 31.25 - def __init__(self, device="xc6slx9", programmer="xc3sprog"): - self.programmer = programmer + def __init__(self, device="xc6slx9"): XilinxPlatform.__init__(self, device+"-3-ftg256", _io, _connectors) def create_programmer(self): - if self.programmer == "xc3sprog": - return XC3SProg("minispartan6", "bscan_spi_minispartan6.bit") - elif self.programmer == "fpgaprog": - return FpgaProg() - else: - raise ValueError("{} programmer is not supported".format( - self.programmer)) + return FpgaProg() diff --git a/litex/boards/platforms/nexys4ddr.py b/litex/boards/platforms/nexys4ddr.py index f3bd2183..359d6ec3 100644 --- a/litex/boards/platforms/nexys4ddr.py +++ b/litex/boards/platforms/nexys4ddr.py @@ -86,20 +86,12 @@ class Platform(XilinxPlatform): default_clk_name = "clk100" default_clk_period = 10.0 - def __init__(self, programmer="vivado"): + def __init__(self): XilinxPlatform.__init__(self, "xc7a100t-CSG324-1", _io, toolchain="vivado") - self.programmer = programmer self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]") - def create_programmer(self): - if self.programmer == "xc3sprog": - return XC3SProg("nexys4") - elif self.programmer == "vivado": - return VivadoProgrammer() - else: - raise ValueError("{} programmer is not supported" - .format(self.programmer)) + return VivadoProgrammer() def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex/boards/platforms/nexys_video.py b/litex/boards/platforms/nexys_video.py index 3ed2c0c1..67570412 100644 --- a/litex/boards/platforms/nexys_video.py +++ b/litex/boards/platforms/nexys_video.py @@ -215,26 +215,18 @@ class Platform(XilinxPlatform): default_clk_name = "clk100" default_clk_period = 10.0 - def __init__(self, toolchain="vivado", programmer="vivado"): - XilinxPlatform.__init__(self, "xc7a200t-sbg484-1", _io, _connectors, - toolchain=toolchain) + def __init__(self): + XilinxPlatform.__init__(self, "xc7a200t-sbg484-1", _io, _connectors, toolchain="vivado") self.toolchain.bitstream_commands = \ ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] self.toolchain.additional_commands = \ ["write_cfgmem -force -format bin -interface spix4 -size 16 " "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] - self.programmer = programmer self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]") def create_programmer(self): - if self.programmer == "xc3sprog": - return XC3SProg("nexys4") - elif self.programmer == "vivado": - return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4") - else: - raise ValueError("{} programmer is not supported" - .format(self.programmer)) + return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex/boards/platforms/tinyfpga_bx.py b/litex/boards/platforms/tinyfpga_bx.py index 0c022817..d3bd3264 100644 --- a/litex/boards/platforms/tinyfpga_bx.py +++ b/litex/boards/platforms/tinyfpga_bx.py @@ -54,8 +54,7 @@ class Platform(LatticePlatform): default_clk_period = 62.5 def __init__(self): - LatticePlatform.__init__(self, "ice40-lp8k-cm81", _io, _connectors, - toolchain="icestorm") + LatticePlatform.__init__(self, "ice40-lp8k-cm81", _io, _connectors, toolchain="icestorm") def create_programmer(self): return TinyProgProgrammer() -- 2.30.2