From cba63fe72b27c135e5fe04560d3a625e82c65fe3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 9 Sep 2019 22:06:23 -0700
Subject: [PATCH] Oops

---
 passes/pmgen/xilinx_dsp.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 7bac1b974..d48c646c0 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -192,6 +192,7 @@ void pack_xilinx_simd(Module *module, const std::vector<Cell*> &selected_cells)
 		SigSpec Y = lane->getPort("\\Y");
 		A.extend_u0(24, lane->getParam("\\A_SIGNED").as_bool());
 		B.extend_u0(24, lane->getParam("\\B_SIGNED").as_bool());
+		C.append(A);
 		AB.append(B);
 		if (GetSize(Y) < 25)
 			Y.append(module->addWire(NEW_ID, 25-GetSize(Y)));
-- 
2.30.2