From cba68605e927fca7e7a32f006453c763da3032ab Mon Sep 17 00:00:00 2001
From: Michael Nolan <mtnolan2640@gmail.com>
Date: Sun, 5 Apr 2020 14:00:44 -0400
Subject: [PATCH] Fix addi instruction, think a commit got lost

---
 src/soc/decoder/isa/caller.py      |  6 ++++--
 src/soc/decoder/isa/test_caller.py | 12 +++++++++++-
 src/soc/decoder/selectable_int.py  |  4 ++++
 3 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index de54143b..874a0697 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -88,9 +88,11 @@ class ISACaller:
 
     def prep_namespace(self):
         si = yield self.decoder.SI
-        self.namespace.SI = SelectableInt(si, bits=16)
+        self.namespace['SI'] = SelectableInt(si, bits=16)
 
     def call(self, name):
+        yield from self.prep_namespace()
+
         function, read_regs, uninit_regs, write_regs = self.instrs[name]
         input_names = create_args(read_regs | uninit_regs)
         print(input_names)
@@ -108,7 +110,7 @@ class ISACaller:
         for name, output in zip(output_names, results):
             regnum = yield getattr(self.decoder, name)
             print('writing reg %d' % regnum)
-            self.gpr[regnum] = output
+            self.gpr[regnum] = output.narrow(64)
 
 
 def inject():
diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index 73692f00..aa6f23ae 100644
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -60,10 +60,20 @@ class DecoderTestCase(FHDLTestCase):
             sim = self.run_test_program(program, initial_regs)
             self.assertEqual(sim.gpr(1), SelectableInt(0x5555, 64))
 
-    def run_test_program(self, prog, initial_regs):
+    def test_addi(self):
+        lst = ["addi 3, 0, 0x1234",
+               "addi 2, 0, 0x4321",
+               "add  1, 3, 2"]
+        with Program(lst) as program:
+            sim = self.run_test_program(program)
+            print(sim.gpr(1))
+            self.assertEqual(sim.gpr(1), SelectableInt(0x5555, 64))
+
+    def run_test_program(self, prog, initial_regs=[0] * 32):
         simulator = self.run_tst(prog, initial_regs)
         simulator.gpr.dump()
         return simulator
 
+
 if __name__ == "__main__":
     unittest.main()
diff --git a/src/soc/decoder/selectable_int.py b/src/soc/decoder/selectable_int.py
index fb064fcb..28e48f2e 100644
--- a/src/soc/decoder/selectable_int.py
+++ b/src/soc/decoder/selectable_int.py
@@ -159,6 +159,10 @@ class SelectableInt:
             return onebit(other == self.value)
         assert False
 
+    def narrow(self, bits):
+        assert bits <= self.bits
+        return SelectableInt(self.value, bits)
+
     def __bool__(self):
         return self.value != 0
 
-- 
2.30.2