From cbb23a1d3c3df9d6bed34f50a0193b93319477e6 Mon Sep 17 00:00:00 2001 From: Daniel Johnson Date: Tue, 13 Sep 2011 12:06:13 -0500 Subject: [PATCH] ARM: update TLB to set request packet ASID field --- src/arch/arm/miscregs.hh | 5 +++++ src/arch/arm/tlb.cc | 2 ++ src/arch/arm/tlb.hh | 2 +- 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 5e5735de7..1f84fa4ca 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -436,6 +436,11 @@ namespace ArmISA Bitfield<31,30> or7; EndBitUnion(NMRR) + BitUnion32(CONTEXTIDR) + Bitfield<7,0> asid; + Bitfield<31,8> procid; + EndBitUnion(CONTEXTIDR) + BitUnion32(L2CTLR) Bitfield<2,0> sataRAMLatency; Bitfield<4,3> reserved_4_3; diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 942f85120..a03e445cf 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -467,6 +467,8 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, bool is_write = (mode == Write); bool is_priv = isPriv && !(flags & UserMode); + req->setAsid(contextId.asid); + DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n", isPriv, flags & UserMode); // If this is a clrex instruction, provide a PA of 0 with no fault diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index f78e38a3d..3464e42b3 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -222,7 +222,7 @@ class TLB : public BaseTLB protected: SCTLR sctlr; bool isPriv; - uint32_t contextId; + CONTEXTIDR contextId; PRRR prrr; NMRR nmrr; uint32_t dacr; -- 2.30.2