From cbd7e976519c1e53bdd7316acb5ca0feb269bd2d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 4 May 2021 17:32:26 +0100 Subject: [PATCH] add SVSRR0 to FastRegsEnum --- src/soc/regfile/regfiles.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py index 1f45ab91..26abc779 100644 --- a/src/soc/regfile/regfiles.py +++ b/src/soc/regfile/regfiles.py @@ -90,7 +90,7 @@ class IntRegs(RegFileMem): #class IntRegs(RegFileArray): class FastRegs(RegFileMem, FastRegsEnum): #RegFileArray): """FastRegs - FAST regfile - CTR, LR, TAR, SRR1, SRR2, XER, TB, DEC + FAST regfile - CTR, LR, TAR, SRR1, SRR2, XER, TB, DEC, SVSRR0 * QTY 6of 64-bit registers * 3R2W -- 2.30.2