From cc2236d0c02be096ad1b92209072be3f16598933 Mon Sep 17 00:00:00 2001 From: Jeff Wang Date: Thu, 16 Jan 2020 17:11:08 -0500 Subject: [PATCH] lexer doesn't seem to return TOK_REG for logic anymore --- frontends/verilog/verilog_parser.y | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 08db36276..ea0a09599 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1261,13 +1261,14 @@ enum_type: TOK_ENUM { enum_base_type: int_vec param_range | int_atom - | /* nothing */ { addRange(astbuf1); } + | /* nothing */ {astbuf1->is_reg = true; addRange(astbuf1); } ; -int_atom: TOK_INTEGER { addRange(astbuf1); } // probably should do byte, range [7:0] here +int_atom: TOK_INTEGER {astbuf1->is_reg=true; addRange(astbuf1); } // probably should do byte, range [7:0] here ; -int_vec: TOK_REG { astbuf1->is_reg = true; } // lexer returns this for logic|bit too +int_vec: TOK_REG {astbuf1->is_reg = true;} + | TOK_LOGIC {astbuf1->is_logic = true;} ; enum_name_list: -- 2.30.2