From cc3e12b504c20b3bc78db52059d3f4f9b02dfbe8 Mon Sep 17 00:00:00 2001
From: Gabe Black <gabeblack@google.com>
Date: Sun, 12 Apr 2020 22:05:00 -0700
Subject: [PATCH] arm: Don't use pseudo instructions to implement regular
 instructions.

Some ARM instructions were using quiesce and quiesceSkip pseudo
instruction bodies instead of implementing the one line of each of those
functions themselves. This creates two problems. First, it adds an
artificial depedence on the pseudo instruction implementations. Second,
it would confusing cause pseudo instruction DPRINTFs to fire when normal
instructions were executing.

This change simply replaces the calls with their targets one line
implementation, with some very minor duplication from multiple call
sights factored out into a local variable.

Change-Id: I596eafd8714227fa7f69edd542108598c9809b11
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27790
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/arch/arm/isa/insts/misc.isa     | 16 +++++++++-------
 src/arch/arm/isa/templates/pred.isa |  6 ++++--
 2 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index b2f459158..64bf791d5 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -721,18 +721,19 @@ let {{
 
     // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending,
     ThreadContext *tc = xc->tcBase();
+    Tick next_cycle = tc->getCpuPtr()->nextCycle();
     if (SevMailbox == 1) {
         SevMailbox = 0;
-        PseudoInst::quiesceSkip(tc);
+        tc->quiesceTick(next_cycle + 1);
     } else if (tc->getCpuPtr()->getInterruptController(
                 tc->threadId())->checkInterrupts()) {
-        PseudoInst::quiesceSkip(tc);
+        tc->quiesceTick(next_cycle + 1);
     } else {
         fault = trapWFx(tc, cpsr, scr, true);
         if (fault == NoFault) {
-            PseudoInst::quiesce(tc);
+            tc->quiesce();
         } else {
-            PseudoInst::quiesceSkip(tc);
+            tc->quiesceTick(next_cycle + 1);
         }
     }
     '''
@@ -760,15 +761,16 @@ let {{
     ThreadContext *tc = xc->tcBase();
     auto *ic = dynamic_cast<ArmISA::Interrupts *>(
             tc->getCpuPtr()->getInterruptController(tc->threadId()));
+    Tick next_cycle = tc->getCpuPtr()->nextCycle();
     if (ic->checkWfiWake(hcr, cpsr, scr)) {
-        PseudoInst::quiesceSkip(tc);
+        tc->quiesceTick(next_cycle + 1);
     } else {
         fault = trapWFx(tc, cpsr, scr, false);
         if (fault == NoFault) {
-            PseudoInst::quiesce(tc);
+            tc->quiesce();
             ArmSystem::callSetStandByWfi(tc);
         } else {
-            PseudoInst::quiesceSkip(tc);
+            tc->quiesceTick(next_cycle + 1);
         }
     }
     tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index ee48f90cd..9b08fc3d3 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -206,7 +206,8 @@ def template QuiescePredOpExecute {{
             }
         } else {
             xc->setPredicate(false);
-            PseudoInst::quiesceSkip(xc->tcBase());
+            ThreadContext *tc = xc->tcBase();
+            tc->quiesceTick(tc->getCpuPtr()->nextCycle() + 1);
         }
 
         return fault;
@@ -233,7 +234,8 @@ def template QuiescePredOpExecuteWithFixup {{
         } else {
             xc->setPredicate(false);
             %(pred_fixup)s;
-            PseudoInst::quiesceSkip(xc->tcBase());
+            ThreadContext *tc = xc->tcBase();
+            tc->quiesceTick(tc->getCpuPtr()->nextCycle() + 1);
         }
 
         return fault;
-- 
2.30.2