From cc5e379eca3cea2369c49ebf8e554b35614495de Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 18 Oct 2013 13:25:24 +0200 Subject: [PATCH] Added RTLIL NEW_WIRE macro --- kernel/rtlil.cc | 9 +++++++++ kernel/rtlil.h | 4 ++++ 2 files changed, 13 insertions(+) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 6271aeef8..5075215cd 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -382,6 +382,15 @@ RTLIL::Module *RTLIL::Module::clone() const return new_mod; } +RTLIL::SigSpec RTLIL::Module::new_wire(int width, RTLIL::IdString name) +{ + RTLIL::Wire *wire = new RTLIL::Wire; + wire->width = width; + wire->name = name; + add(wire); + return wire; +} + void RTLIL::Module::add(RTLIL::Wire *wire) { assert(!wire->name.empty()); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 7796ce969..a3d1dafd9 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -129,6 +129,9 @@ namespace RTLIL #define NEW_ID \ RTLIL::new_id(__FILE__, __LINE__, __FUNCTION__) +#define NEW_WIRE(_mod, _width) \ + (_mod)->new_wire(_width, NEW_ID) + template struct sort_by_name { bool operator()(T *a, T *b) const { return a->name < b->name; @@ -244,6 +247,7 @@ struct RTLIL::Module { virtual size_t count_id(RTLIL::IdString id); virtual void check(); virtual void optimize(); + RTLIL::SigSpec new_wire(int width, RTLIL::IdString name); void add(RTLIL::Wire *wire); void add(RTLIL::Cell *cell); void fixup_ports(); -- 2.30.2