From cc660c45bccfffadd53fc49e35ee77b7b75da657 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 11 Aug 2022 23:54:32 +0100 Subject: [PATCH] --- openpower/sv/executive_summary.mdwn | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/openpower/sv/executive_summary.mdwn b/openpower/sv/executive_summary.mdwn index 5445125c0..05585c700 100644 --- a/openpower/sv/executive_summary.mdwn +++ b/openpower/sv/executive_summary.mdwn @@ -12,9 +12,9 @@ Power ISA. It is extremely important to think of Simple-V as a 2-Dimensional ISA: instructions vertical and registers horizontal otherwise it will be difficult to grasp and appreciate its RISC simplicity. - Like all Cray-Style Scalable Vector ISAs, Simple-V binaries remain -ubiquitous, the ISA uniform. +ubiquitous, the ISA uniform. The Compliancy Levels offer a means +to scale up in complexity to meet the target application requirements. * GPUs may implement massive-wide SIMD back-ends, focussing on number-crunching. @@ -30,7 +30,7 @@ ecosystem)*. *If not done as carefully as SVP64, the addition of any other Scalable Vector Extension would require a significant number of opcodes, putting further pressure on Major Opcode space which was never designed with -Scalable Vectors in mind in the first place. Contrast with RISC-V which was +Scalable Vectors in mind. Contrast with RISC-V which was designed over a 7 year period with Cray-style Vectors right from the start.* Even with this amount of time spent, SVP64 exceeds the capability of RVV. @@ -66,15 +66,11 @@ hot-loops. |---------------------------------------------------------------------------------------------| | **Unit tests and simulator for Power ISA v3.0 and SVP64** | | | -| - - - | | **pypowersim tutorial** | | | -| - - - | | **several thousand more ISA unit tests** | | | -| - - - | | **demo, showing 4.5x reduction in program size for MP3 decode, greatly simplifies assembler development** | | | -| - - - | | **binutils support for SVP64** | | | -- 2.30.2