From cc8c158dae72b645d473e8f4b45214557568dcd5 Mon Sep 17 00:00:00 2001 From: Kajol Jain Date: Tue, 11 Jun 2019 15:39:17 +0530 Subject: [PATCH] arch-power: Added PIR register * Added PIR(Processor Identification Register). * Added mfpir instruction to get content of register PIR. Change-Id: I16b82684e7c9a5e5172f0395dd0a021791757425 Signed-off-by: Kajol Jain --- src/arch/power/isa/decoder.isa | 2 +- src/arch/power/isa/operands.isa | 1 + src/arch/power/registers.hh | 5 +++-- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa index b2647ce59..dbf8810d5 100644 --- a/src/arch/power/isa/decoder.isa +++ b/src/arch/power/isa/decoder.isa @@ -630,7 +630,7 @@ decode PO default Unknown::unknown() { 0x3c9: mflpcr({{Rt = LPCR;}}); 0x3E8: mfpvr({{ Rt = PVR; }}); 0x3e9: mflpidr({{Rt = LPIDR;}}); - + 0x3ff: mfpir({{ Rt = PIR;}}, [ IsPrivileged ]); } 467: decode SPR { 0x004: mttfhar({{TFHAR = Rs;}}); diff --git a/src/arch/power/isa/operands.isa b/src/arch/power/isa/operands.isa index 7b8aaa081..41a4fbb0a 100644 --- a/src/arch/power/isa/operands.isa +++ b/src/arch/power/isa/operands.isa @@ -147,6 +147,7 @@ def operands {{ 'IC': ('IntReg', 'ud', 'INTREG_IC', 'IsInteger' , 9), 'VTB': ('IntReg', 'ud', 'INTREG_VTB', 'IsInteger' , 9), 'HSPRG1': ('IntReg', 'ud', 'INTREG_HSPRG1', 'IsInteger' , 9), + 'PIR': ('IntReg', 'uw', 'INTREG_PIR', 'IsInteger' , 9), # Setting as IntReg so things are stored as an integer, not double 'FPSCR': ('IntReg', 'uw', 'INTREG_FPSCR', 'IsFloating', 9), diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh index bee4671bd..ad5820bdf 100644 --- a/src/arch/power/registers.hh +++ b/src/arch/power/registers.hh @@ -68,7 +68,7 @@ const int NumIntArchRegs = 32; // CR, XER, LR, CTR, TAR, FPSCR, RSV, RSV-LEN, RSV-ADDR // and zero register, which doesn't actually exist but needs a number -const int NumIntSpecialRegs = 87; +const int NumIntSpecialRegs = 88; const int NumFloatArchRegs = 32; const int NumFloatSpecialRegs = 0; const int NumInternalProcRegs = 0; @@ -188,7 +188,8 @@ enum MiscIntRegNums { INTREG_ASDR, INTREG_IC, INTREG_VTB, - INTREG_HSPRG1 + INTREG_HSPRG1, + INTREG_PIR }; } // namespace PowerISA -- 2.30.2