From cc9239c1236bb9685fb57903a0ecee589199483e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 30 Jul 2020 15:12:05 +0100 Subject: [PATCH] core_start/stop/endian were inverted (output) --- src/soc/simple/issuer.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index c45bb28a..854a5e66 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -74,9 +74,9 @@ class TestIssuer(Elaboratable): # busy/halted signals from core comb += self.busy_o.eq(core.busy_o) comb += self.halted_o.eq(core.core_terminated_o) - comb += self.core_start_i.eq(core.core_start_i) - comb += self.core_stop_i.eq(core.core_stop_i) - comb += self.core_bigendian_i.eq(core.bigendian_i) + comb += core.core_start_i.eq(self.core_start_i) + comb += core.core_stop_i.eq(self.core_stop_i) + comb += core.bigendian_i.eq(self.core_bigendian_i) # temporary hack: says "go" immediately for both address gen and ST l0 = core.l0 -- 2.30.2