From cca0653285271f948dcd05640628f1a82c73ec37 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 10 Jun 2020 12:33:38 +0100 Subject: [PATCH] ilang file output change from alu_pipeline.il to div_pipeline.il --- src/soc/fu/div/test/test_pipe_caller.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py index 2e66f90a..4a25a5fa 100644 --- a/src/soc/fu/div/test/test_pipe_caller.py +++ b/src/soc/fu/div/test/test_pipe_caller.py @@ -190,7 +190,7 @@ class DIVTestCase(FHDLTestCase): pspec = DIVPipeSpec(id_wid=2) alu = DIVBasePipe(pspec) vl = rtlil.convert(alu, ports=alu.ports()) - with open("alu_pipeline.il", "w") as f: + with open("div_pipeline.il", "w") as f: f.write(vl) -- 2.30.2