From cca815b0861d56e8705d0a074b9717123e745a09 Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Thu, 9 Jul 2020 15:08:30 +0200 Subject: [PATCH] Add test for SoC readout --- gram/test/test_soc.py | 53 +++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 51 insertions(+), 2 deletions(-) diff --git a/gram/test/test_soc.py b/gram/test/test_soc.py index 0f33a65..3813bf4 100644 --- a/gram/test/test_soc.py +++ b/gram/test/test_soc.py @@ -1,6 +1,7 @@ # This file is Copyright (c) 2020 LambdaConcept from nmigen import * +from nmigen.asserts import Assert, Assume from nmigen_soc import wishbone, memory from nmigen.lib.cdc import ResetSynchronizer @@ -99,7 +100,55 @@ class SocTestCase(FHDLTestCase): m.submodules += soc def process(): - #res = yield from wb_read(soc.bus, 0x10000000 >> 2, 0xF, 16384) - yield + yield from wb_write(soc.bus, 0x0, 0xE, 0xF) # DFII_CONTROL_ODT|DFII_CONTROL_RESET_N|DFI_CONTROL_CKE + yield from wb_write(soc.bus, 0xC >> 2, 0x0, 0xF) + yield from wb_write(soc.bus, 0x10 >> 2, 0x0, 0xF) + yield from wb_write(soc.bus, 0x0, 0xC, 0xF) + + yield from wb_write(soc.bus, 0x0, 0xE, 0xF) + + # MR2 + yield from wb_write(soc.bus, 0xC >> 2, 0x200, 0xF) + yield from wb_write(soc.bus, 0x10 >> 2, 0x2, 0xF) + yield from wb_write(soc.bus, 0x4 >> 2, 0xF, 0xF) + yield from wb_write(soc.bus, 0x8 >> 2, 0x1, 0xF) + + # MR3 + yield from wb_write(soc.bus, 0xC >> 2, 0x0, 0xF) + yield from wb_write(soc.bus, 0x10 >> 2, 0x3, 0xF) + yield from wb_write(soc.bus, 0x4 >> 2, 0xF, 0xF) + yield from wb_write(soc.bus, 0x8 >> 2, 0x1, 0xF) + + # MR1 + yield from wb_write(soc.bus, 0xC >> 2, 0x6, 0xF) + yield from wb_write(soc.bus, 0x10 >> 2, 0x1, 0xF) + yield from wb_write(soc.bus, 0x4 >> 2, 0xF, 0xF) + yield from wb_write(soc.bus, 0x8 >> 2, 0x1, 0xF) + + # MR0 + yield from wb_write(soc.bus, 0xC >> 2, 0x320, 0xF) + yield from wb_write(soc.bus, 0x10 >> 2, 0x0, 0xF) + yield from wb_write(soc.bus, 0x4 >> 2, 0xF, 0xF) + yield from wb_write(soc.bus, 0x8 >> 2, 0x1, 0xF) + + for i in range(200): + yield + + # ZQ + yield from wb_write(soc.bus, 0xC >> 2, 0x400, 0xF) + yield from wb_write(soc.bus, 0x10 >> 2, 0x0, 0xF) + yield from wb_write(soc.bus, 0x4 >> 2, 0x3, 0xF) + yield from wb_write(soc.bus, 0x8 >> 2, 0x1, 0xF) + + for i in range(200): + yield + + yield from wb_write(soc.bus, 0, 0x1, 0xF) + + for i in range(2000): + yield + + res = yield from wb_read(soc.bus, 0x10000000 >> 2, 0xF, 16384) + self.assertEqual(res, 0xDEADBEEF) runSimulation(m, process, "test_soc.vcd") -- 2.30.2